MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 138

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 56: READ Latency (AL = 5, CL = 6)
Mode Register 2 (MR2)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
BC4
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
READ n
(MIN) = CL, a typical application using this feature sets AL = CL - 1
t
internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of
the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS
WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 138)). Exam-
ples of READ and WRITE latencies are shown in Figure 56 (page 138) and Figure 58
(page 139).
The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL), AU-
TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT
(R
programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR2 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time
sequent operation.
T1
CK. The READ or WRITE command is held for the time of the AL before it is released
TT(WR)
t RCD (MIN)
). These functions are controlled via the bits shown in Figure 57. The MR2 is
AL = 5
NOP
T2
RL = AL + CL = 11
NOP
T6
138
CL = 6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T11
NOP
Indicates A Break in
Time Scale
1Gb: x4, x8, x16 DDR3 SDRAM
t
MRD and
NOP
T12
Mode Register 2 (MR2)
DO
n
t
MOD before initiating a sub-
© 2006 Micron Technology, Inc. All rights reserved.
Transitioning Data
n + 1
DO
t
CK =
NOP
T13
n + 2
DO
t
RCD (MIN) - 1
n + 3
DO
Don’t Care
NOP
T14