MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 201
![IC DDR3 SDRAM 1GBIT 78FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT41J256M4HX-15E:D TR
Manufacturer Part Number
MT41J256M4HX-15E:D TR
Description
IC DDR3 SDRAM 1GBIT 78FBGA
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Specifications of MT41J256M4HX-15E:D TR
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
1G (256M x 4)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-FBGA
Organization
256Mx4
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
220mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 201 of 208
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Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period oc-
curs if the DLL is selected to be off when in precharge power-down mode by the setting
MR0[12] = 0. Power-down entry begins
and it ends when CKE is first registered LOW.
+ 1
gress when CKE goes LOW, power-down entry will end
mand rather than when CKE is first registered LOW. Power-down entry will then
become the greater of
ODT assertion during power-down entry results in an R
of
(MAX) and ODTL on ×
may result in an R
t
Table 88 (page 202) summarizes these parameters.
If the AL has a large value, the uncertainty of the state of R
is because ODTL on and ODTL off are derived from the WL and WL is equal to CWL +
AL. Figure 119 (page 202) shows three different cases:
• ODT_A: Synchronous behavior before
• ODT_B: ODT state changes during the transition period with
• ODT_C: ODT state changes after the transition period with asynchronous behavior
AOF (MIN) or as late as the greater of
ODTL on ×
(MAX)
t
t
AONPD (MIN) and ODTL on ×
CK or ODTL on + 1
t
CK +
TT
t
AON (MIN) and
change as early as the lesser of
t
t
t
CK. If a REFRESH command has been issued, and it is in pro-
ANPD and
CK +
t
201
AON (MAX). ODT deassertion during power-down entry
t
t
CK +
RFC - REFRESH command to CKE registered LOW.
t
AONPD (MAX) greater than ODTL on ×
t
AOFPD (MAX) and ODTL off ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
ANPD prior to CKE first being registered LOW,
AON (MIN) or as late as the greater of
t
ANPD
t
ANPD is equal to the greater of ODTL off
1Gb: x4, x8, x16 DDR3 SDRAM
t
AOFPD (MIN) and ODTL off ×
t
TT
RFC after the REFRESH com-
TT
change as early as the lesser
becomes quite large. This
© 2006 Micron Technology, Inc. All rights reserved.
t
AONPD (MIN) less than
t
CK +
t
AOF (MAX).
t
CK +
t
AONPD
t
t
AON
CK +
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