MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 122

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 46: Change Frequency During Precharge Power-Down
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
DQS, DQS#
Command
Address
ODT
DM
CK#
CKE
DQ
CK
NOP
T0
t AOFPD/ t AOF
t IH
t CH
t CK
power-down mode
Enter precharge
t CL
t IS
Notes:
NOP
Previous clock frequency
T1
t CPDED
High-Z
High-Z
1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
2.
3. If the R
t CKSRE
NOP
T2
t
tion (ODT) (page 187) for exact requirements).
down mode, the ODT signal must be continuously registered LOW ensuring R
off state. If the R
charge power-down mode, R
registered either LOW or HIGH in this case.
AOFPD and
TT,nom
Ta0
t CKE
t
feature was enabled in the mode register prior to entering precharge power-
AOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina-
Frequency
change
TT,nom
Tb0
feature was disabled in the mode register prior to entering pre-
122
t CKSRX
Tc0
t IH
TT
t CH
b
t CK
will remain in the off state. The ODT signal can be
power-down mode
b
Exit precharge
t CL
b
t IS
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
Tc1
Input Clock Frequency Change
1Gb: x4, x8, x16 DDR3 SDRAM
New clock frequency
NOP
Td0
t XP
t CH
b
t CK
b
t CL
DLL RESET
b
MRS
Td1
© 2006 Micron Technology, Inc. All rights reserved.
Indicates A Break in
Time Scale
t DLLK
NOP
Te0
t IH
t CH
b
t CK
b
t CL
b
TT
t IS
Valid
Valid
Te1
is in an
Don’t Care