MT41J256M4HX-15E:D TR Micron Technology Inc, MT41J256M4HX-15E:D TR Datasheet - Page 174

• Manufacturer Part Number: MT41J256M4HX-15E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M4HX-15E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Organization: 256Mx4
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRECHARGE Operation
SELF REFRESH Operation
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
Input A10 determines whether one bank or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
The SELF REFRESH operation is initiated like a REFRESH command except CKE is
LOW. The DLL is automatically disabled upon entering SELF REFRESH and is automati-
cally enabled and reset upon exiting SELF REFRESH.
All power supply inputs (including V
els upon entry/exit and during self refresh mode operation. V
drive V
• V
• V
• The first WRITE operation may not occur earlier than 512 clocks after V
• All other self refresh mode exit timing requirements are met
The DRAM must be idle with all banks in the precharge state (
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see On-Die Termination (ODT) (page 187) for timing re-
quirements). If R
“Don’t Care.” After the self refresh entry command is registered, CKE must be held LOW
to keep the DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, become “Don’t Care.” The DRAM initiates a minimum of one REFRESH
command internally within the
The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting
t
the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit
self refresh mode after
later than when CKE was registered LOW). Since the clock remains stable in self refresh
mode (no frequency change),
clock is altered during self refresh mode (turned-off or frequency change), then
and
fied prior to altering the clock's frequency. Prior to exiting self refresh mode,
must be satisfied prior to registering CKE HIGH.
When CKE is HIGH during self refresh exit, NOP or DES must be issued for
is required for the completion of any internal refresh that is already in progress and
must be satisfied before a valid command not requiring a locked DLL can be issued to
the device.
mand requiring a locked DLL can be applied, a ZQCL command must be issued,
t
t
CK specifications) when self refresh mode is entered. If the clock remains stable and
ZQoper timing must be met, and
XSDLL.
SS
REFDQ
t
CKSRX must be satisfied. When entering self refresh mode,
< V
DDQ
REFDQ
is valid and stable prior to CKE going back HIGH
/2 while in the self refresh mode under certain conditions:
t
XS is also the earliest time self refresh reentry may occur. Before a com-
< V
TT,nom
DD
is maintained
t
and R
CKESR is satisfied (CKE is allowed to transition HIGH
174
TT(WR)
t
CKSRE and
t
CKE period when it enters self refresh mode.
t
XSDLL must be satisfied. ODT must be off during
are disabled in the mode registers, ODT can be a
REFCA
Micron Technology, Inc. reserves the right to change products or specifications without notice.
and V
t
CKSRX are not required. However, if the
1Gb: x4, x8, x16 DDR3 SDRAM
REFDQ
) must be maintained at valid lev-
PRECHARGE Operation
REFDQ
t
© 2006 Micron Technology, Inc. All rights reserved.
RP is satisfied and no
t
CKSRE must be satis-
may float or not
REFDQ
t
XS time.
t
CKSRX
t
CKESR
is valid
t
CKSRE
t
XS