HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 99

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

Section 16 Appendix shows terminal response to all
possible subaddress and mode code command com-
binations. The table summarizes terminal response for
the full range of message conditions, including errors,
incomplete messages, etc. The table explicitly describes
terminal response and impact on terminal Status Word,
Descriptor Control Words and data buffer Message In-
formation Words. The table includes effects for all per-
tinent setup options and identifies all interrupt options
available. Bold text blocks indicate error-free messages
or “in form” Clear Status responses when the terminal is
not using “illegal command detection”.
13. INTERRUPT MANAGEMENT
13.1. Host Message Detection Options
Upon receiving messages, the host has several options.
The individual descriptor table Control Words have en-
able flags for generating interrupts. Interrupts can be
enabled on a subaddress or mode code basis. For any
subaddress, interrupts can be enabled for (a) every
command occurrence, (b) upon occurrence of broadcast
commands, (c) at end of multiple message block trans-
fers (index mode or circular buffer modes only), or (d) no
interrupts at all.
Some subaddress commands may not require immedi-
ate host servicing. If the number of legal subaddresses
is small, the host can poll descriptor table Control Words
for the legal subaddresses to detect message activ-
ity. The Control Word’s DBAC bit (descriptor block ac-
cessed) is set whenever a message is processed. This
bit is automatically reset by any host read cycle to the
descriptor Control Word. Whenever the DBAC bit reads
high, the subaddress transacted a message since the
last Control Word read cycle.
Another interrupt alternative that works for any number
of legal subaddresses (or when illegal command detec-
tion is not used) is to poll the device ACTIVE pin. This
pin is high whenever a command is being processed.
After the ACTIVE pin goes low, the host can read the
Current Command Register to determine the processed
command word, or may fetch the command’s descriptor
table address from the Current Control Word Address
register. Both registers maintain their loaded values until
the next valid command to the terminal is decoded.
Descriptor Words 2 and 3, and Descriptor Word 1
(bits 9, 11) are also updated.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
99
13.2. Host Interrupt Generation
Interrupts are output signals notifying the host when
predetermined events have occurred during terminal op-
eration; the interrupt-causing events are fully program-
mable. The host defines message-specific interrupt-
causing events when initializing the Descriptor Table.
Other hardware-based interrupts are configured when
internal device registers are initialized.
To manage host interrupts, the device architecture in-
volves an Interrupt Log buffer, three control registers,
two interrupt output pins and two interrupt acknowledge
input pins. The three internal registers are the Pending
Interrupt Register, the Interrupt Enable Register and the
Interrupt Log Address Register. The Pending Interrupt
Register contains information identifying events pro-
grammed by the host to generate interrupts. The Inter-
rupt Enable register lets the host enable or disable in-
terrupt generation for different interrupt-causing events.
The Interrupt Log Buffer is a 32-word ring buffer located
in shared RAM address range 0x0040 to 0x005F.
Separate interrupt outputs are provided for hardware
interrupts (INTHW) and message interrupts (INTMES).
The host programs both pins as either pulsed interrupt
outputs or level-sensitive outputs, by writing the INTSEL
bit in Configuration Register 1. The states are summa-
rized in Table 10.
Pulsed outputs have brief (~250ns) duration, sufficient
to drive edge-triggered host inputs. In the level mode
of operation, asserted interrupts remain low until ac-
knowledged by the host. There are two ways the host
can acknowledge level interrupts: (1) assert the ACKHW
or ACKMES input pin to clear the respective interrupt
INTHW or INTMES output, or (2) read the Pending Inter-
rupt Register to clear both INTHW and INTMES output
pins to the high state.
Assertion of the INTHW interrupt indicates an interrupt-
causing hardware event that is enabled in the Interrupt
Register 1
Table 10. Summary of Interrupt Outputs.
Config.
INTSEL
Bit
0
1
Pulsed Output
Output Pins
Level Output
Active Low
Active Low
Interrupt
INTMES
INTHW
Acknowledge Input
(Internal pull-downs)
The ACK pins are
Active High
ACKMES
Interrupt
not used
ACKHW
Pins