HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 42

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

This register supports two types of test: Register bits 15 - 8 are used for RAM built-in self test (RAM BIST). Register
bits 7 - 2 are used for transceiver loopback testing (either digital loopback or analog loopback).
Under internal logic control, this device uses one RAM self test (Inc / Dec Test described below) to check internal RAM
memory after MR pin master reset. Test Control Register bits 15 - 8 provide a means for the host to perform RAM
self-test at other times. Register bits 13:11 select RAM test type. Then bit 10 starts the selected RAM test, and bits
9-8 report a pass/fail result after test completion. All tests are destructive, overwriting data present before test com-
mencement.
NOTE: ‘Reset’ refers to bit value following either Master Reset (MR) or software reset.
13,12,11 RBSEL2:0
MSB
Bit No.
15
14
15 14 13 12 11 10 9
Mnemonic
FRAMA
RBFFAIL
R/W Reset Function
R/W
R/W
R/W
8
7
0
0
0
0
0
6
Full RAM Access Enable.
During normal operation, some bits in certain RAM locations (e.g., Descrip-
tor Table Control Words) cannot be written by the host. When the FRAMA
bit is asserted, host writes to RAM are unrestricted to permit full testing.
During normal completion, this bit must be reset to logic 0.
RAM BIST Force Failure.
When this bit is asserted, RAM test failure is forced to verify that RAM BIST
logic is functional.
RAM BIST Select Bits 2-0.
This 3-bit field selects the RAM BIST test mode applied when the RB-
START bit is set:
5
RBSEL2:0 Selected RAM Test
HOLT INTEGRATED CIRCUITS
4
000
001
010
100
101
011
110
111
HI-6120, HI-6121
3
2
1
Idle
Pattern Test, described below
Write 0x0000 to RAM address range 0x0000 -
0x7FFF
Read and verify 0x0000 over RAM address range
0x0000 - 0x7FFF
Write 0xFFFF to RAM address range 0x0000 -
0x7FFF
Read and verify 0xFFFF over RAM address range
0x0000 - 0x7FFF
Inc / Dec Test performs only steps 5 - 8 of the Pat-
tern Test below
Idle
0
42
LSB
14.42ms
1.32ms
170μs
500μs
170μs
500μs
Time
Test
-
-