HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 36

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

5.12. Memory Address Pointer Register (HI-6121 only) (0x000F)
This register is Read-Write and is cleared after MR pin master reset, but is not affected by SRST software
reset. This register is maintained by the host. The contained value is a memory address used when fulfilling RAM or
register read or write operations via the HI-6121 Serial Peripheral Interface (SPI). See data sheet section, ”Host Serial
Peripheral Interface (SPI)” for further details. For HI-6120 devices, writes to this address have no effect; the address
reads back 0x0000 if a host read cycle occurs.
5.13. Interrupt Enable Register (0x0010)
This 16-bit register is Read-Write (except bits 2-0 are read only) and is fully maintained by the host. All bits are active
high. For further information on interrupts, see descriptions for the Pending Interrupt and Interrupt Log Address regis-
ters, and refer to the later section entitled “Interrupt Management”.
An interrupt type is globally disabled when the corresponding bit in this register is reset. This allows the external host
or subsystem to temporarily disable interrupt servicing for some or all interrupts. While an interrupt enable bit is ne-
gated, the terminal does not generate an interrupt output signal for the corresponding interrupt event. Note: Asserting
an interrupt bit in this register after an event occurs does not generate an interrupt for that event. For some interrupts
that result from message processing, interrupt enable bits in a each command’s descriptor Control Word act in combi-
nation with settings in this register to respond appropriately to interrupt-causing events.
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset.
Bit No. Mnemonic
MSB
MSB
15
14
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
IXEQZ
IWA
X
X
MEMORY ADDRESS 15:0
R/W
R/W
R/W
X
8
8
8
Reset
7
7
7
0
0
6
6
6
5
5
5
Function
Index Equal Zero Interrupt.
When this bit is asserted, interrupts are globally enabled for (a) subad-
dresses using indexed buffer mode when the index decrements from 1 to
0, and (b) subaddresses using a circular buffer mode when the pre-deter-
mined number of messages has been transacted. When this bit is assert-
ed, occurrence of an IXEQZ event (a) or (b) causes INTMES output asser-
tion (if the IXEQZ bit is set in the command’s descriptor Control Word).
Interrupt When Accessed Interrupt.
When this bit is asserted, interrupts are globally enabled for each message
occurrence to subaddresses in which the Descriptor Control Word allows
the IWA interrupt. When this bit is asserted, occurrence of an IWA event
causes INTMES output assertion (if the IWA bit is set in the command’s
descriptor Control Word).
HOLT INTEGRATED CIRCUITS
4
4
4
HI-6120, HI-6121
3
3
3
2
2
1
2
1
1
1
1
0
1
0
0
36
LSB
LSB