HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 13

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

ACKMES*
ACKHW*
BENDI
Pin
CE
* Note: These pins are combined into the ACKINT pin on HI-6121PQx variant.
Function
INPUT
INPUT
INPUT
INPUT
Description
Chip Enable, active low. Internal 50KΩ pull-up resistor. When asserted, this pin
enables host read or write accesses to device RAM or registers. On HI-6121, it is
normally connected to a host SPI slave select output signal.
Configuration pin for selecting “endianness” of the host interface when byte trans-
fers are used. Internal 50KΩ pull-up resistor. Endianness is the system attribute
that indicates whether integers are represented with the most significant byte
stored at the lowest address (big endian) or at the highest address (little endian).
Internal storage is “big endian.” When using the HI-6120, this pin only applies
when the host bus is configured for 8-bit width, that is, when BWID equals 0.
When the HI-6120 is configured for 16-bit bus width, the BENDI input pin is “don’t
care.” When using the HI-6121, this pin controls the byte order of the 16-bit data
following the SPI command.
When BENDI is low, “little endian” is chosen; the low order byte (bits 7:0) is trans-
acted before the high order byte (bits 15:8). When BENDI is high, “big endian” is
chosen and the high order byte is transacted on the host bus before the low order
byte.
Hardware Interrupt Acknowledge, active high. Internal 50KW pull-down resistor.
This input is only used when the INTSEL bit in Configuration Register 1 is assert-
ed to enable level interrupts. After interrupt assertion causes the INTHW output
to go low, a high state (60ns minimum duration) on ACKHW will clear the INTHW
output to logic 1. The interrupt is also cleared automatically by reading the Pend-
ing Interrupt Register.
Message Interrupt Acknowledge, active high. Internal 50KW pull-down resistor.
This input is only used when the INTSEL bit in Configuration Register 1 is as-
serted to enable level interrupts. After interrupt assertion causes the INTMES
output to go low, a high state (60ns minimum duration) on ACKMES will clear the
INTMES output to logic 1. The interrupt is also cleared automatically by reading
the Pending Interrupt Register.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
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