HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 41

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

5.18. Alternate Built-in Test Word Register (0x0015)
This 16-bit register is Read-Write and is fully maintained by the external host. This register is cleared after MR pin
master reset but is unaffected by SRST software reset.
If the ALTBITW option bit in Configuration Register 2 equals one when a valid “transmit BIT word” mode command
(MC19) is received, the current value in this register is transmitted as the mode data word in the terminal response.
The value is also copied to the assigned data buffer for MC19, after mode command fulfillment.
5.19. Reserved Register (0x0016)
Register 0x0016 is used for factory testing. It is cleared after MR pin master reset and cannot be written by the
host while the TEST input pin is low.
5.20. Test Control Register (0x0017)
This register controls RAM built-in self-test, and transceiver loopback testing. Bits 0, 1, 8, 9 are Read Only. The re-
maining bits in this register are Read-Write but can be written only when the TEST input pin is high. If TEST = 0, these
bits will read back 0x0000.
Bit No. Mnemonic R/W
MSB
3
2
1
0
15 14 13 12 11 10 9
15 14 13 12 11 10 9
BMTF
RTAPF
EELF
TFBINH
ALTERNATE BUILT-IN TEST WORD REGISTER15:0
R
R
R
R
Result
Result
Result
Reset
SR = 0
8
8
Test
Test
Test
0
7
7
6
6
Function
BIST Memory Test Fail (see Section 5.20).
This bit is set if error occurs during built-in self-test for device RAM memory.
RT Address Parity Failure.
This bit is asserted when Operational Status Register bits 15:10 reflect parity
error. After MR master reset, bits 15:10 in the Operational Status Register
reflect input pin states, but will be overwritten if subsequent auto-initialization
is performed (if AUTOEN pin is high) and the initialization EEPROM contains
different data for Operational Status Register bits 15:10.
Auto-Initialization EEPROM Load Fail.
This bit only applies when auto-initialization is enabled (AUTOEN input pin
state equals 1). This bit is set if, after MR master reset, failure occurs when
copying serial EEPROM to registers and RAM. When this occurs, bit 0 or bit
1 will be set in the Operational Status Register (0x0002) to indicate type of
failure.
Terminal Flag Bit Inhibited.
This bit is set when the Terminal Flag status bit is disabled while fulfilling
an “inhibit terminal flag bit” mode code command (MC6). This bit is reset if
terminal flag status bit disablement is later cancelled by an “override inhibit
terminal flag bit” mode code command (MC7).
5
5
HOLT INTEGRATED CIRCUITS
4
4
HI-6120, HI-6121
3
3
2
2
1
1
0
0
41
LSB