HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 22

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

11, 10, 9 TTCK2:0
Bit No.
6,5
12
8
7
Mnemonic R/W
SDSEL
STEX
SRST
-----
R/W
R/W
R/W
R/W
R/W
(SR = 0)
(SR = 0)
Reset
0
0
0
0
0
Function
Shutdown Select.
This bit affects terminal response to “transmitter shutdown” mode code
commands and only applies when the MCOPT4 bit in Configuration
Register 2 equals logic 0 for automatic shutdown after “transmitter shut-
down” and “selected transmitter shutdown” mode code commands. When
MCOPT4 and SDSEL are both logic 0, a valid “transmitter shutdown”
mode command automatically disables the inactive bus transmitter and
receiver (complete ”bus shutdown”). This is the recommended mode of
operation and is the default state of these two bits after MR reset.
When MCOPT4 is logic 0 and SDSEL is logic 1, “transmitter shutdown” or
“selected transmitter shutdown” mode commands automatically disable
just the inactive bus transmitter, but the bus receiver remains enabled.
The terminal fully complies with valid commands received on the inactive
bus (storing received data, etc.), except it does not transmit status or data
onto that bus (”mute terminal”). This mode of operation is not recommend-
ed but may be required in some applications. See MCOPT4 bit in Configu-
ration Register 2 for further information concerning “transmitter shutdown”
and “selected transmitter shutdown” mode commands. The Built-In Test
(BIT) Word Register contains status flags that reflect automatic shutdown
status when the MCOPT4 bit in Configuration Register 2 is logic 0. See
page xx.
Time-Tag Counter Clock Select. These three bits select the time-tag coun-
ter clock source from the following options:
Start Execution.
Assertion of this bit initiates RT operation; negation of this bit inhibits or
stops RT operation. Upon STEX assertion, RT parity-address error pre-
vents terminal operation, regardless of the logical state of the STEX bit.
If RT address parity error occurs, the Status Register and Pending Inter-
rupt Register RTAPF bits will be asserted. This bit is cleared after MR pin
master reset.
Software Reset.
Assertion of this bit immediately initiates the software reset process. This
bit should not be set to logic 1 during auto-initialization. This bit is cleared
after MR master reset and automatically self-resets after being set by the
host.
Not used.
TTCK2
HOLT INTEGRATED CIRCUITS
0
0
0
0
1
1
1
1
HI-6120, HI-6121
TTCK1
0
0
1
1
0
0
1
1
22
TTCK0
0
1
0
1
0
1
0
1
Clock Source
Time-Tag counter disabled
External clock provided at TTCK input pin
Internally generated 2μs clock
Internally generated 4μs clock
Internally generated 8μs clock
Internally generated 16μs clock
Internally generated 32μs clock
Internally generated 64μs clock