HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 24

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

5.2.
This 16-bit register is Read-Write and is fully maintained by the host. All bits are active high.
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset.
Bit No.
MSB
15,14
13
12
15 14 13 12 11 10 9
Configuration Register 2 (0x0001)
Mnemonic
TOSEL1:0
TRXDB
TTLOAD
R/W Reset Function
R/W
R/W
R/W
8
0
0
0
7
6
Time-Out Select for RT-RT Receive Commands.
These bits select the “no response” time-out for RT-RT receive commands.
Message error occurs when the transmitting Remote Terminal fails to begin
transmission before time-out occurs. Time interval boundaries are defined in
RT validation test plan Figure 8 “RT-RT Timeout Measurement.” MIL-STD-
1553B stipulates that 54 to 60μs is the acceptable range for time-out. How-
ever, longer time-out options are provided for systems using long buses and/
or utilizing bus repeaters that add delay to bus traffic. RT-RT time-out can be
selected from the following options:
Temporary Receive Data Buffer.
Setting this bit enables a temporary data buffer for all receive commands.
When enabled, the RT stores received data words in a 32-word data buffer
during message processing. Upon error-free message completion, all saved
words are written to data buffer memory in a burst. When the temporary
receive data buffer is disabled, the RT writes each received data word to the
subaddress data buffer memory as it is received. Should message error oc-
cur during data word reception, this mode results in loss of data integrity, as
vaild data from the prior command is partially overwritten by data from a mes-
sage with error. MIL-STD-1553 states that data should be disregarded for
messages ending in error. This bit should only be modified while Configura-
tion Register 1 STEX bit is low. Changes occurring while STEX = 1 cause un-
predictable results. In a typical application, the buffer is not directly accessed
by the host, although there is no restriction preventing host data access.
Load Time-Tag Counter.
When this bit is written from logic 0 to logic 1, data contained in the Time-
Tag Utility register is written to the Time-Tag counter. The TTLOAD register
bit self-resets after use. See MCOPT3 bit which affects automatic Time-Tag
counter loading upon “synchronize” mode command with data word.
5
TOSEL1
HOLT INTEGRATED CIRCUITS
X
4
1
1
0
0
HI-6120, HI-6121
X
3
X
2
X
1
TOSEL0
X
0
24
LSB
1
0
1
0
RT-RT Time-Out
150μs
125μs
100μs
57μs
reset)
(default after MR pin master