HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 32

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

Bit No. Mnemonic R/W Reset Function
6,5
10
9
8
7
4
3
2
1
MERR
-----
ILCMD
SPIFAIL
LBFA,
LBFB
TTINT1
TTINT0
RTAPF
EECKF
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
Message Error Interrupt.
If the MERR bit is set in the Interrupt Enable register, this bit is asserted when
a message error is detected. Errors can be caused by Manchester encoding
problems or protocol errors. The INTMES output is asserted and the Interrupt
Log is updated.
Not used.
Illegal Command Interrupt.
If the ILCMD bit is set in the Interrupt Enable register, this bit is asserted each
time an illegal message (determined by the Illegalization Table) occurs for a
new command. The INTMES output is asserted and the Interrupt Log is up-
dated. See section “Illegalization Table” for additional information.
SPI Fail Interrupt (HI-6121 only).
The HI-6121 uses a SPI interface for host access. The device operates in SPI
Slave mode. If the SPIFAIL bit is set in the Interrupt Enable register, this bit
is asserted each time an incorrect number of SCK clocks occurs during SPI
chip select assertion, The INTHW output is asserted and the Interrupt Log is
updated.
Loopback Fail Bus A and Loopback Fail Bus B Interrupts.
During all transmitted command responses, the device compares words trans-
mitted to the received and decoded words detected on the bus. If the LBFA or
LBFB bit is set in the Interrupt Enable register, this bit is asserted each time
this loopback detects mismatch. The INTMES output is asserted and the Inter-
rupt Log is updated.
Time-Tag Interrupt 1.
If the TTINT1 bit is set in the Interrupt Enable register, this bit is asserted each
time the free-running Time-Tag counter value matches the value stored in the
Time-Tag Utility Register. The INTHW output is asserted and the Interrupt Log
is updated.
Time-Tag Interrupt 0.
If the TTINT0 bit is set in the Interrupt Enable register, this bit is asserted each
time the free-running Time-Tag counter value rolls over from full count 0xFFFF
to 0x0000. The INTHW output is asserted and the Interrupt Log is updated.
RT Address Parity Fail Interrupt.
This bit is asserted when RT address and parity bits latched in the Operational
Status Register do not exhibit odd parity (odd number of bits having logic 1
state). Because the RTAPF bit is always set in the Interrupt Enable register,
the INTHW output is asserted and the Interrupt Log is updated. When par-
ity error occurs, the RT will not begin operation, regardless of the state of the
Control Register STEX bit.
Initialization EEPROM Checksum Fail Interrupt.
This bit is asserted if serial EEPROM checksum failure occurs during auto-
initialization. Because the EECKF bit is always set in the Interrupt Enable
register, the INTHW output is asserted and the Interrupt Log is updated.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
32