hi-3599pst Holt Integrated Circuits, Inc., hi-3599pst Datasheet
hi-3599pst
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hi-3599pst Summary of contents
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... FPGA. The SPI and all control signals are CMOS and TTL compatible and support 3. operation. The HI-3599 is identical to the HI-3598 except not all pins are available. This allows a minimum package footprint to be achieved with only slightly less hardware flexibility. FEATURES · ...
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... Control Register BUS 8 BUS 7 BUS 6 BUS 5 BUS 4 BUS 3 40 Kohm BUS 2 { RIN1A ARINC 429 40 Kohm RIN1B BUS 1 The 40 Kohm resistors are shorted on the HI-3599-40 HI-3598, HI-3599 VDD Label Filter Memory ARINC 429 Label Valid word Filter Checker ...
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... Read the contents of the label memory for this channel Read an ARINC word from the receive FIFO for this channel. If the FIFO is empty all zeros will be read Load the specified channel’s Control Register and clear that channel’s FIFO Read the specified channel’ ...
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... HI-3598, HI-3599 STATUS REGISTER The HI-3598 and HI-3599 have a single 16-bit Status Register which is read to determine status for the eight received data FIFOs. The Status Register is read using SPI instruction n6 hex. The following table defines the Status Register bits: SR FUNCTION ...
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... Valid data bits require at least three consecutive One or Zero samples (three high bits) in the upper half of the Ones or Ze- ros sampling shift register, and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift register within the data bit interval ...
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... Receive FIFO. ARINC words that do not match required 9th and 10th ARINC bit and do not have a label match are ignored and are not loaded into the Receive FIFO. The adjacent table describes this operation. SCK CS SI ...
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... ARINC 429 bus. The first bit shifted into the Self Test register will be the first bit sent to the receivers and the TX1 and TX0 pins. In ARINC 429 protocol, this bit is the LSB ...
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... SCK SI SO HI-3598, HI-3599 SERIAL INPUT TIMING DIAGRAM t CES t t SCKR DH MSB SERIAL OUTPUT TIMING DIAGRAM t DV MSB RECEIVER OPERATION t t SPIF RXR SPI INSTRUCTION n3 hex ARINC HOLT INTEGRATED CIRCUITS 8 t CPH t t SCKF CEH LSB t CPH t CHZ LSB Hi Impedance WORD ...
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... NUL Differential GND Input Sink I IH Input Source I IL Differential C (RINA to RINB GND Input Voltage Input Sink I IH Input Source pin Output Sink ...
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... SPI SI Data hold time after SCK rising edge SO high-impedance after SCK falling edge RECEIVER TIMING Delay - Last bit of received ARINC word to FLAG(Full or Empty Speed Delay - Last bit of received ARINC word to FLAG(Full or Empty Speed Received data available to SPI interface. FLAG to HEAT SINK - CHIP-SCALE PACKAGE ONLY ...
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... RIN3B - GND - Pin Plastic Small Outilne Package HOLT INTEGRATED CIRCUITS 11 HI-3599PCx- RIN7B-40 HI-3599PCI- RIN7A- RIN6B-40 HI-3599PCT- RIN6A- RIN5B- RIN5A- Chip-Scale Package (QFN) HI-3599PSx- VDD 23 - FLAG - RIN8B -40 HI-3599 21 - RIN8A -40 PSI- RIN7B -40 & RIN7A - RIN6B -40 HI-3599 - 8 ...
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... Tin / Lead (Sn / Pb) Solder Blank 100% Matte Tin (Pb-free, RoHS compliant) F TEMPERATURE FLOW RANGE I -40°C TO +85°C T -55°C TO +125°C PACKAGE DESCRIPTION PC 44 PIN PLASTIC CHIP-SCALE PKG, QFN (44PCS PIN PLASTIC WIDE SOIC (24HW) HOLT INTEGRATED CIRCUITS 12 BURN BURN IN I ...
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... REVISION HISTORY Revision Date Page Description of Change DS3598, Rev. NEW 06/12/08 All HI-3598, HI-3599 Initial Release HOLT INTEGRATED CIRCUITS 13 ...
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... PLASTIC QUAD FLAT PACK (PQFP) .520 BSC SQ (13.2) .063 (1.6) See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .354 BSC (9.00) .354 Top View BSC (9.00) .039 max (1.00) HI-3598 PACKAGE DIMENSIONS .394 BSC SQ (10 ...
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... PLASTIC SMALL OUTLINE (SOIC (Wide Body) (Wide Body) .407 ± .013 (10.325 ± .32) .050 BSC (1.27) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) .276 Top View BSC (7.00) .039 max (1.00) BSC = “ ...