HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 34

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

5.9.
This register is Read Only and is cleared after MR pin Master Reset or SRST software reset. Reads to this
register address return the current value of the free running 16-bit Time Tag counter. Counter resolution is programmed
by TTCK2:0 bits in Configuration Register 1. Options are: 2, 4, 8, 16, 32 and 64us, or externally provided clock.
The device automatically resets the Time-Tag count when a “synchronize” mode command without data (MC1) is
received. In addition, the host can reset the Time-Tag count at any time by asserting the RTTAG bit in Configuration
Register 2.
The MCOPT2 and MCOPT3 bits in Configuration Register 2 allow automatic loading of Time-Tag count using the
data word received with a “synchronize with data” mode command, MC17. If both of these bits equal one, the data
word received with a valid “synchronize” mode command (MC17) is unconditionally loaded into the Time-Tag counter.
For non-broadcast MC17 commands, the counter load occurs before status word transmission. If both MCOPT2 and
MCOPT3 bits equal 0, the external host assumes responsibility for actions needed to perform “synchronize” duties
upon reception of the valid MC17 “synchronize” command, but status transmission automatically occurs.
The binary 01 and 10 combinations of the MCOPT2 and MCOPT3 bits support certain extended subaddressing
schemes. If the MCOPT3-MCOPT2 bits equal 01, the received data word is automatically loaded into the Time-Tag
counter if the low order bit of the received data word (bit 0) equals 0. If the MCOPT3-MCOPT2 bits equal 10, the re-
ceived data word is automatically loaded into the Time-Tag counter if the low order bit of the received data word (bit 0)
equals 1. For non-broadcast MC17 commands, the counter load occurs before status word transmission.
Bit No. Mnemonic
MSB
3
2
1
0
15 14 13 12 11 10 9
15 14 13 12 11 10 9
Time-Tag Register (0x0008)
BUSY
SSYSF
-----
TF
TIME-TAG COUNT 15:0
R/W
R/W
R/W
R/W
R
8
8
Reset
7
7
0
0
0
0
6
6
5
5
Function
Busy (global).
When this bit is asserted, the device asserts Busy bit in status response for
all valid commands. Instead of globally enabling Busy status for all com-
mands here, the host can assert Busy status for selected commands by
asserting the Busy bit in descriptor table Control Words for the individual
commands. When response to a command conveys Busy status, the
device suppresses transmission of data words that would normally accom-
pany status transmission. For any message transacted with Busy status,
the WASBUSY flag is asserted in the stored Message Information Word.
Subsystem Flag.
This register bit is logically ORed with the SSYSF input pin. If either SSYSF
register bit or SSYSF pin is asserted, the SSYSF Subsystem Flag status
bit is set. If the Configuration Register 2 MCOPT1 bit equals 0, reception of
a “transmit vector word” mode command (MC16) causes automatic reset
of the SSYSF status bit in this register; when this occurs, the register bit is
reset before status word transmission begins.
Not used, this bit cannot be set.
Terminal Flag.
When this bit is asserted, the Terminal Flag status bit is set.
HOLT INTEGRATED CIRCUITS
4
4
HI-6120, HI-6121
3
3
2
2
1
1
0
0
34
LSB