HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 108

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

Data prefetch during read cycles is blocked when the
next RAM address is a Control Word in the Descrip-
tor Table. The table base address (set by the value in
register 0x0005) and every fourth word thereafter is a
Control Word. This consists of table addresses having
these address offsets from the table start address of 0,
4, 8, 0xC… 0x1F8 and 0x1FC. If allowed, prefetch (like
any other read) would reset the Control Word DBAC sta-
tus bit, so prefetch is disallowed in this range. Thus for
HI-6120, multi-word sequential read sequences will
assert WAIT every fourth word when reading RAM
within the 512-word Descriptor Table address range.
For fastest read access under all conditions, the user
can set host processor bus timing (by adjusting proces-
sor wait states for the chip select assigned to the HI-
6120) to match the faster read cycle time for prefetched
data, while the HI-6120 WAIT output adds one or more
additional wait states for the slower initial read cycle.
Timing diagrams for bus read and write operations are
shown in Section 17.5. Separate diagrams show “Intel
style” and “Motorola style” control interfaces.
15.2. HI-6121 Serial Peripheral Interface
In the HI-6121, internal RAM and registers occupy a 32K
x 16 address space. The lowest 32 addresses access
registers and the remaining addresses access RAM lo-
cations. Timing is identical for register operations and
RAM operations via the serial interface, and read and
write operations have likewise identical timing.
Figure 18. Generalized Single-Byte Transfer Using SPI Protocol. SCK is Shown for SPI Modes 0
SCK (SPI Mode 0)
SCK (SPI Mode 3)
SI
SO
CE
High Z
MSB
MSB
0
0
1
1
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
2
2
and 3
108
3
3
15.2.1. Serial Peripheral Interface (SPI) Basics
The HI-6121 uses an SPI synchronous serial interface
for host access to registers and RAM. Host serial com-
munication is enabled through the Chip Enable (CE) pin,
and is accessed via a three-wire interface consisting of
Serial Data Input (SI) from the host, Serial Data Output
(SO) to the host and Serial Clock (SCK). All program-
ming cycles are completely self-timed, and no erase
cycle is required before write.
The SPI (Serial Peripheral Interface) protocol specifies
master and slave operation; the HI-6121 operates as an
SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-
CPHA combinations define four possible “SPI Modes.”
Without describing details of the SPI modes, the HI-
6121 operates in the two modes where input data for
each device (master and slave) is clocked on the rising
edge of SCK, and output data for each device changes
on the falling edge. These are known as SPI Mode 0
(CPHA = 0, CPOL = 0) and SPI Mode 3 (CPHA = 1,
CPOL = 1). Be sure to set the host SPI logic for one of
these modes.
4
4
5
5
6
6
LSB
LSB
7
7
High Z