HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 38

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

The Interrupt Enable Register lets the host temporarily or permanently disable interrupt servicing for some or all in-
terrupt types. When bits are reset in this register, interrupt output signals are globally disabled for the corresponding
interrupt types. Asserting a bit in the Interrupt Enable register after an event occurs does not generate an interrupt
for that event. The IXEQZ, IWA and IBR interrupts result from message processing. The host can enable or disable
these three interrupt types for individual subaddresses and mode code commands by setting or resetting the IXEQZ,
IWA and IBR bits in descriptor table Control Words corresponding to each subaddress or mode command. While the
ILCMD and MERR interrupts also result from message processing, these interrupts (along with all hardware interrupts)
are globally enabled or disabled, and are unaffected by descriptor table settings. Table gives a summary of settings
and responses to interrupt-causing messages.
5.14. Time-Tag Utility Register (0x0011)
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master
reset, but is not affected by SRST software reset. This register has two functions associated with the free-running
Time-Tag counter:
Bit No. Mnemonic
Descriptor Control Word
IXEQZ, IWA & IBR Bits
3
2
1
0
All Interrupts Except
(no Control Word bits)
IXEQZ, IWA & IBR
TTINT0
RTAPF
EECKF
RAMIF
Reset
Set
Set
Table 5. Settings and Responses to Interrupt-Causing Messages
R/W
R/W
SETTING
R
R
R
Interrupt Enable Register
Reset
Bit for Interrupt Type
0
1
1
1
Don’t Care
Function
Time-Tag Interrupt 0.
If this bit is logic 1, the INTHW interrupt output is asserted and the TTINT0
bit is set in the Pending Interrupt register each time the free-running Time-
Tag counter value rolls over from 0xFFFF full count to 0x0000.
RT Address Parity Fail Interrupt.
When this bit is high, the INTHW interrupt is asserted when RT address
parity error is detected. This bit is 1 after MR master reset and cannot be
reset by host register write.
Initialization EEPROM Checksum Fail Interrupt.
When this bit is high, the INTHW interrupt is asserted if serial EEPROM
checksum failure occurs during auto-initialization. This bit is 1 after MR
master reset and cannot be reset by host register write.
RAM Initialization Fail Interrupt.
When this bit is high, the INTHW interrupt is asserted after auto-initializa-
tion if an initialized RAM location does not match its 2 corresponding serial
EEPROM locations. This bit is 1 after MR master reset and cannot be reset
by host register write.
Reset
Reset
HOLT INTEGRATED CIRCUITS
Set
Set
HI-6120, HI-6121
38
in Pending Interrupt Register
Effect on Corresponding Bit
Pending Int. Register bit is set
Pending Int. Register bit is set
No Change
No Change
No Change
RESPONSE
Is Interrupt Output
Signal Generated
Yes
Yes
No
No
No