HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 17

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

within the Descriptor Table itself. Just six defined mode
commands transfer a data word; thus, option 2 is often
preferred since initialization is easier. Consistent, pre-
dictable terminal responses can be set up for all mode
commands, including the reserved and undefined mode
codes. An option bit in Configuration Register 1 glob-
ally sets whether the 22 undefined mode commands
are treated as illegal (RT response dependent on com-
mand’s Illegalization Table setting) or invalid (no RT re-
sponse whatsoever, and no RT status change).
3.1.5.
The device maintains information from the last 16 inter-
rupts in a 32-word circular buffer in shared RAM known
as the Interrupt Log. Two 16-bit words characterize each
interrupt; one word identifies the interrupt type (Interrupt
Identification Word) and one word identifies the com-
mand that generated the interrupt (Interrupt Address
Word). After reset, the Interrupt Log Address Register is
reset to the fixed starting address of the 32 word Inter-
rupt Log. After each occurring interrupt, the device up-
dates the register to point to the log address used for the
next occurring interrupt.
3.2.
3.2.1.
A 50 MHz master clock input is required. The Time-Tag
counter clock is selected from six internally generated
frequencies, or may use an external clock input signal.
3.2.2.
The 5-bit Remote Terminal address is set using pins
RTA0 to RTA4. The RTAP input pin should be set or re-
set to present matching odd parity. The state of the RT
address and parity pins is latched into the Operational
Status register upon rising edge on the MR master reset
input. The state of the LOCK input is latched into the Op-
erational Status register at the same time, and controls
whether or not the active terminal address and parity
in the Operational Status register can be overwritten by
host writes into the register. Between Master Reset as-
sertions, the state of the RTA and RTAP inputs is “don’t
care”. If the value of RT address and parity in the Opera-
tional Status register has parity error, terminal operation
is disallowed.
3.2.3.
A free-running 16-bit counter provides time-tag values
that are recorded for each message transacted. The
time-tag counter can be clocked from one of six inter-
Hardware Feature Summary
Interrupt Log
Clock Interrupts
Remote Terminal Address Inputs
Integral Time-Tag Counter
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
17
nally generated frequencies, or from an external source.
The user can enable automatic counter synchronization
in response to “synchronize” mode commands, and op-
tional host interrupts are provided for time-tag counter
roll-over, and counter match to a stored value in the
Time-Tag Utility register.
3.2.4.
Built-in bus transceivers provide direct interface between
the device and MIL-STD-1553 bus isolation transform-
ers. The transceivers convert digital data to and from
differential Manchester II encoded bus signals. A pair of
“transmit inhibit” input pins exercises direct control over
transmission for both buses.
3.2.5.
The RT contains separate Manchester II encoders and
decoders for each bus. Encoder-decoder logic inter-
faces directly with the dual-bus MIL-STD-1553 trans-
ceivers. The decoder checks for proper sync pulse and
Manchester waveform, edge skew, correct number of
bits and parity. During transmission, each encoded word
is looped back through the decoder to check for errors.
Bus sampling is clocked at 25 MHz, providing superior
tolerance to zero-crossing distortion.
3.2.6.
The device has an automatic self-initialization feature.
If self-initialization is enabled after MR master reset,
the device reads configuration settings from external
serial EEPROM to load the Descriptor Table, Illegaliza-
tion Table, transmit mode command data and registers
for terminal operation. Self-initialization can optionally
initialize transmit data buffers with fixed data from EE-
PROM. A mechanism is provided to initially program or
later modify the external serial EEPROM memory, by
copying host-loaded tables and register values to the
serial EEPROM.
Dual Bus Transceivers
Encoder and Decoders
Auto-Initialization Serial EEPROM
Interface