HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 28

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

5.3.
All sixteen register bits are active high. After rising edge on the MR master reset input pin, bits 15 - 8 reflect the state
of input pins RTA4 through RTA0, RTAP, LOCK and AUTOEN; register bits 7 - 3 are reset to logic 0 state. Register bits
8 - 0 are always read-only. If the register’s LOCK bit is logic 0, bits 15 - 9 are read-write but cannot be written unless
STEX in Configuration Register 1 is low. If the register LOCK bit is logic 1, bits 15 - 9 are is read-only. Once the LOCK
bit is set, unlock requires a new MR master reset assertion with the LOCK input pin at logic 0 state.
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The value “PIN” denotes the bit is set to the
value of the corresponding pin following Master Reset. This register is unaffected by software reset.
MSB
Bit No.
15-11
10
9
8
7
15 14 13 12 11 10 9
Operational Status Register (0x0002)
Mnemonic R/W
RTA4 - 0
RTAP
LOCK
AUTOEN
READY
R/W
R/W
R/W
R
R
8
Reset
PIN
PIN
PIN
PIN
7
0
6
Function
Remote Terminal Address bits 4 - 0.
Remote Terminal Address Parity.
These bits contain the active remote terminal address. After a rising edge
on the MR master reset input signal, these bits reflect the state of the
RTA4 - 0 and RTAP input pins. When the register LOCK bit is high, these
bits are read-only. When the register LOCK bit is low (and STEX in Con-
figuration Register 1 equals 0) auto-initialization (see bit 8) or the host can
overwrite these bits to change the terminal address and parity.
Terminal Address Lock.
After a rising edge on the MR master reset input signal, this bit reflects the
state of the LOCK input pin. When the LOCK bit is high, this bit is read-only.
When LOCK is low (and STEX in Configuration Register 1 equals 0) auto-
initialization (see bit 8) or the host can write this bit to logic 1 to lock the
active terminal address.
Auto-Initialize Enable.
This read-only bit reflects the state of the AUTOEN input pin that applied at
the rising edge on the MR master reset input signal. If the register AUTOEN
bit is high, device auto-initialization was performed following MR reset.
When auto-initialization is complete, the device waits for the host to as-
sert the STEX bit in Configuration Register 1 to enable terminal operation.
Auto-initialization of the Control Register can optionally set STEX to begin
terminal operation without host assistance. See section entitled “Reset and
Initialization” for details.
Ready status.
This read-only bit reflects the state of the output pin READY and is cleared
on reset. The bit is asserted after post-reset internal terminal initialization is
complete, indicating that shared RAM is ready to accept configuration data
from the host.
5
HOLT INTEGRATED CIRCUITS
4
HI-6120, HI-6121
3
2
1
0
28
LSB