HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 109

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

The difference between SPI Modes 0 and 3 is the idle
state for the SCK signal, which is logic 0 for Mode 0
state and logic 1 for Mode 3 state (see Figure 18). There
is no configuration setting in the HI-6121 to select SPI
Mode 0 or Mode 3 because compatibility is automatic.
Beyond this point, the HI-6121 data sheet only shows
the SPI Mode 0 SCK signal in timing diagrams.
The SPI protocol transfers serial data as 8-bit bytes.
Once CE chip enable is asserted, the next 8 rising edg-
es on SCK latch input data into the master and slave de-
vices, starting with each byte’s most-significant bit. The
HI-6121 SPI can be clocked at 16 MHz.
Multiple bytes may be transferred when the host holds
CE low after the first byte transferred, and continues to
clock SCK in multiples of 8 clocks. A rising edge on CE
chip enable terminates the serial transfer and reinitial-
izes the HI-6121 SPI for the next transfer. If CE goes
high before a full byte is clocked by SCK, the incomplete
byte clocked into the device SI pin is discarded.
Two byte transfers are needed for SPI exchange of 16-
bit register values or RAM data. “Big endian” byte order
is used for SPI data transfers. The high order byte (bits
15:8) is transferred before the low order byte (bits 7:0).
In the general case, both master and slave simulta-
neously send and receive serial data (full duplex) per
Figure 18 below. However the HI-6121 operates half
duplex, maintaining high impedance on the SO output,
except when actually transmitting serial data. When the
HI-6121 is sending data on SO during read operations,
activity on its SI input is ignored. Figure 19 and Figure
20 show actual behavior for the HI-6121 SO output.
15.2.2. HI-6121 SPI Commands
For the HI-6121, each SPI read or write operation be-
gins with an 8-bit command byte transferred from the
host to the device after assertion of CE. Since HI-6121
command byte reception is half-duplex, the host dis-
cards the dummy byte it receives while serially transmit-
ting the command byte.
The HI-6121 SPI command set uses the most significant
command bit to specify whether the command is Read
or Write. The command byte MSB is zero for read com-
mands, and one for write commands.
15.2.3. Fast-Access Commands for Registers
The SPI command set includes directly-addressed read
and write commands for registers 0 through 15. The
8-bit pattern for these commands has the general form
0-15
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
109
where RRRR is the 4-bit register address, and the most
significant bit, W signifies Write when 1, or Read when
0. These fast-access commands appear in Table 13.
Figure 19 and Figure 20 show read and write timing as
it appears for fast-access register operations. The com-
mand byte is immediately followed by two data bytes
comprising the 16-bit data word read or written. For a
register read or write, CE is negated after the 2-byte
data word is transferred.
15.2.4. Indirect Addressing of RAM and
Refer to the HI-6121 SPI command set shown in Table
14. SPI commands other than fast-access use an ad-
dress pointer to indicate the address for read or write
transactions. This “memory address pointer” resides at
register address 15, and must be initialized before any
read or write operation, other than fast-access.
To set the address pointer, use a fast-access write to
register 15, consisting of command byte 0xBC followed
by the desired 16-bit memory or register address. The
pointer uses a 15-bit value to access any location in the
32K address range. The current address pointer value
can be read using a fast-access read command byte
0x3C.
After a 2-byte read/write completion, the internal address
pointer automatically increments to the following
register address. The host can extend the read or write
operation to the next register address by continuing to
hold CE low while clocking SCK 16 additional times.
This auto-increment feature can be used to access
one or more sequential register addresses above the
command address. Auto-increment applies (ranging to
the top of the address space) as long as SCK continues
to be clocked under continuous CE assertion. Caution:
When the primary address pointer is used for auto-
incrementing multi-word read/write and reaches the top
of the address range (0x7FFF) the next increment will
roll over the pointer value to 0x0000. The host should
avoid this situation.
Registers
W-0-R-R-R-R-0-0