HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 105

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

14.2. Software Reset
Software reset is initiated by a host write that sets the
SRST bit in Configuration Register 1. This bit is set au-
tomatically when a “Reset Remote Terminal” mode com-
mand is received while the MCOPT0 bit is set in Con-
figuration Register 2 (0x0002). Software reset causes
immediate reset without overwriting registers or tables
that were initialized by the host to define terminal behav-
ior. Changes to registers and RAM are summarized in
Table 12. Software reset cannot initiate automatic self-
initialization from serial EEPROM. Once the SRST bit in
Configuration Register 1 is asserted, the following steps
are performed:
1. The READY, ACTIVE, INTMES and INTHW output
2. The Descriptor Base Address register (0x0005) is
3. The BIT Word Register (0x0014) is cleared, except
4. All 128 descriptor table Control Words are modified
5. The device asserts the READY output pin. Terminal
6. After READY assertion, the host may reset STEX,
pins are negated. Terminal execution stops while
SRST reset is underway. Command processing is
terminated. The hardware bus decoders and hard-
ware encoder are cleared. The Message Error and
Broadcast Command Received flags in the internal
status register used for MC2 or MC18 mode com-
mand responses are not affected by SRST.
reinitialized to the base address 0x0200. The follow-
ing registers are cleared: the 1553 Status Word Bits
register (0x0007), the Time-Tag register (0x0008)
and test registers 0x0016 to 0x0019.
the contained RTAPF bit is not changed. This rein-
states any bus previously shutdown by mode code
commands MC4 or MC20 (decimal). If the Terminal
Flag status bit was previously inhibited by mode
command MC6, inhibit is cleared: The Terminal Flag
status bit will be transmitted whenever bit 0 is set in
the 1553 Status Word Bits Register.
to reset the DBAC, DPB, MKBUSY and BCAST bits.
Subaddresses or mode codes using ping-pong or
single message index mode (INDX = 0) are ready for
immediate operation after SRST reset is complete.
However the device cannot reinitialize the Descrip-
tor Table to restore multi-message block transfers,
for indexed buffer mode when initial INDX value
was non-zero, or for either circular buffer mode.
operation automatically resumes if the STEX bit in
Configuration Register 1 was set before SRST oc-
curred.
then reinitialize all or part of the Descriptor Table.
The host can reinitialize the Descriptor Table for
subaddresses using multi-message block transfers
(Circular Buffer Mode 1, Circular Buffer Mode 2 or
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
105
14.3. Reset Remote Terminal Mode Code
Mode code MC8 with T/R bit = 1 should reset the Re-
mote Terminal. After Status Word transmission, the
device automatically resets the status Message Error
(ME) and Broadcast Command received (BCR) bits in
its internal status register. Bits 0, 14 and 15 are reset in
the BIT Word register at address 0x0014. If either trans-
mitter was shutdown by a previous mode code MC4
or MC20, the shutdown condition is overridden. If the
Terminal Flag (TF) status bit was inhibited, the inhibit
is reset. This command does not reset any of the host-
programmed registers that configure the terminal for op-
eration.
To complete the reset process, the host must assert ei-
ther MR master reset (with or without auto-initialization)
or assert the SRST bit in Configuration Register 1 to ex-
ecute software reset. Since MC8 requires host interac-
tion, most applications will probably utilize the IWA inter-
rupt to alert the host when valid MC8 is received.
Per MIL-STD-1553B appendix 30.4.3, any reset initiated
by the “Reset Remote Terminal” mode command should
be completed within 5 ms following transmission of the
Status Word. Overall reset time includes internal device
initialization, either host initialization or auto-initializa-
tion. Overall time to complete reset initiated by the “Re-
set Remote Terminal” mode command MC8 is affected
by host response speed and application complexity.
14.4. Serial EEPROM Programming Utility
The HI-6120 or HI-6121 can program a serial EEPROM
via the dedicated EEPROM SPI port for subsequent
auto-initialization events. The device copies host-config-
ured registers and RAM (configuration tables and pos-
sibly data buffers) to serial EEPROM.
Compatible SPI serial EEPROMs are 3.3V, operate in
SPI modes 1 or 3 and and have 128-byte pages. The
serial SPI data is clocked at 8.3 MHz SCK frequency. A
2K x 8 EEPROM can restore the lower 1K x 16 device
address space. A 64K x 8 EEPROM can restore the
entire 32K x 16 device address space.
Indexed Buffer Mode with initial non-zero INDX.)
The host can also reinitialize transmit data in the
assigned transmit subaddress data buffers. Data
buffers in RAM contain data values loaded before
SRST occurred. The host can clear or overwrite this
old data. The host can then assert the STEX bit in
Configuration Register 1 to restart terminal opera-
tion.