HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 101

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

14. RESET AND INITIALIZATION
This section describes the hardware and software re-
set mechanisms. Hardware Master Reset returns the
device to the uninitialized state, requiring register/RAM
initialization before terminal execution can begin. Initial-
ization can be performed by the host after MR reset, or
automatically, at the user’s option, by reading configu-
ration data from an external serial EEPROM. Software
reset is asserted by setting the SRST bit in Configura-
tion Register 1. Software reset has minimal effect on
previously initialized registers and RAM structures that
define terminal behavior. However some reinitialization
may be needed for some applications, after SRST reset
is complete.
14.1. Master Reset using the MR pin and
Hardware master reset is initiated by a low to high tran-
sition on the MR pin; it should be applied after power-up,
but may be used anytime afterward. When asserted, the
MR input pin causes immediate, unconditional hardware
reset. Command processing is terminated, the bus de-
coders and encoder are cleared, the Time-Tag count is
reset. The Message Error, Busy and Broadcast Com-
mand Received status bits are reset and Terminal Flag
bit is enabled for assertion. All internal logic is cleared.
Registers and RAM structures are restored to the states
shown in Table 12. The READY, ACTIVE, INTMES and
INTHW output pins are negated if previously asserted.
After MR pin low to high transition, these steps occur:
1. After 200ns, the states of the following input pins are
2. If the MTSTOFF pin is logic zero, the device per-
3. After internal processes are initialized, the device
If the Operational Status register AUTOEN bit reads
low, auto-initialization is bypassed. The host must ini-
tialize the terminal as follows:
latched into the Operational Status register: RTA4-
RTA0, RTAP, AUTOEN, LOCK and INTSEL. Before
READY assertion, a host read cycle to any address
returns the value in the Operational Status register.
forms a memory test (< 985us). If memory error oc-
curs, the BMTF bit is set in the BIT Word Register
0x0014. If the MTSTOFF pin is logic one, the mem-
ory test is bypassed. This option might be chosen
if a faster reset process is needed. Regardless of
MTSTOFF state, all RAM locations above address
0x001F are cleared to 0x0000.
checks the latched state of the AUTOEN bit in the
Operational Status register:
Optional Auto-Initialization
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
101
If the Operational Status register AUTOEN bit reads
high, the device initializes itself from an external serial
EEPROM via the dedicated EEPROM SPI port:
a. The device asserts the READY output pin. This
b. Upon READY assertion, the host should initialize
c. After the host completes initialization, it must as-
The READY output pin remains low while auto-
matic self-initialization proceeds. The device reads
initialization data from the external serial EEPROM
memory, using the dedicated EEPROM SPI port.
Initialization includes all registers, all tables (includ-
ing secondary Descriptor Tables, if used) and can
include initial data written to transmit subaddress
data buffers allocated by the Descriptor Table.
During auto-initialization, the written value for each
register or RAM location is read back for confirma-
tion. If the read-back value does not match the cor-
responding value from EEPROM, an initialization
error is saved. This error results in action (described
below) that occurs when the initialization process is
finished.
While performing initialization, a running checksum
is tallied as follows, using EEPROM data read from
the 1K or 32K address range. A properly configured
serial EEPROM contains a 16-bit checksum value
stored at the pair of EEPROM locations correspond-
state change indicates the host can begin post-
MR reset initialization of registers and RAM struc-
tures.
configuration and option registers, the Descriptor
Table(s) and the Illegalization Table. Initialization
may include data written into the various trans-
mit subaddress buffers assigned by the initialized
Descriptor Table.
sert the STEX (start execution) bit in Configura-
tion Register 1 to begin Remote Terminal opera-
tion.
If the EE1K pin is low, initialization covers the
full 32K address range 0x0 to 0x7FFF, including
the entire RAM. Therefore it can initialize second-
ary Descriptor Tables and transmit subaddress
buffers in the upper RAM space. (Note: Typical
auto-initialization time is 63ms).
If the EE1K pin is high, initialization covers just
the 1K address range 0x0 to 0x003F. This cov-
ers all registers and the minimum set of required
tables, including the default Descriptor Table from
0x00200 to 0x003FF. For many applications, this
is the only Descriptor Table. (Note: Typical auto-
initialization time is 1.97ms).