HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 106

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

A deliberate series of events initiates copy of data from
HI-6120 or HI-6121 to serial EEPROM. This reduces the
likelihood of accidental EEPROM overwrites. This series
of events must occur to initiate programming:
1. If using a fresh host initialization immediately
2. If using the existing EEPROM configuration as
3. IMPORTANT: Any processing of valid bus com-
4. The host writes one of two 2-part “unlock codes” to
following MR master reset as the basis for EE-
PROM copy: With the AUTOEN, TXINHA and TX-
INHB pins in logic zero state, apply MR master reset
and wait for READY output assertion. Verify that the
INTHW output does not pulse low at READY asser-
tion, indicating likely RT address parity error at the
RTA4:0 and RTAP pins. Using known good param-
eters, the host initializes device registers, the RAM
descriptor table and transmit data buffers (if neces-
sary). Do not assert STEX. Go to step 3.
the baseline for a new EEPROM configuration:
With the AUTOEN pin in logic 1 state and the TX-
INHA and TXINHB pins in logic zero state, apply MR
master reset and wait for READY output assertion.
Verify that the INTHW output does not pulse low
(or go and remain low) at READY assertion. Con-
firm that the RTAPF, EECKF and RAMIF bits are all
logic 0 in the Operational Status Register 0x0002.
If the STEX bit in Configuration Register 1 was set
by auto-initialization, reset it now. Modify register
and RAM values to reflect the new changes. Go to
Step 3.
mands between MR master reset and this point will
cause auto-initialization checksum failure later, due
to non-zero values written to read-only registers as
a result of command processing. The device will not
enter EEPROM copy mode at step 4 if valid com-
mand reception caused ACTIVE output assertion
after MR reset occurred. If set, the STEX bit in Con-
figuration Register 1 also locks-out EEPROM copy
mode at programming step 4.
RAM address 0x0020. The two unlock codes per-
form identical EEPROM programming with the ex-
ception of the programmed state for the STEX bit in
Configuration Register 1.
If auto-initialize should program Configu-
ration Register 1 STEX bit to logic 0, RAM
address 0x0020 is first written 0xA5F0, then a
second load to 0x0020 overwrites the value just
written with 0x5F0A.
If auto-initialize should program Configu-
ration Register 1 STEX bit to logic 1, RAM
OR
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
106
5. The EECOPY input pin is driven high for at least 1
6. When the READY output goes high, EEPROM copy
7. The address range copied during EEPROM pro-
In either case, the two unlock writes must occur
without intervening access to other device address-
es, except Memory Address Pointer 0x000F for HI-
6121.
ms, then driven low. In response, the READY output
goes low while EEPROM memory is written. Pro-
gramming commences. The unlock code at address
0x0020 is cleared, then device register and RAM
contents are written to the serial EEPROM. During
programming, the twos-complemented checksum
is tallied for the entire address range being pro-
grammed (1K or 32K words), excluding addresses
0x0002, 0x0006, 0x0008, 0x0014 and 0x0020. At
EEPROM programming completion, the final check-
sum is stored in the pair of EEPROM locations cor-
responding to device RAM address 0x0020. The
value written to EEPROM is actually the twos-com-
plement of the memory checksum, (CHECKSUM +
1). The value in EEPROM is used for error detection
when performing auto-initialization. (The host can
only access the stored value immediately after an
auto-initialization sequence is performed. The twos-
complement EEPROM checksum value will be cop-
ied into RAM address 0x0020.)
is complete. The STEX bit is reset in device Con-
figuration Register 1.
gramming depends on the state of the EE1K input
pin when rising edge occurs on the EECOPY input:
If EE1K is high when EECOPY is asserted, the
lower 1K x 16 address range from 0x0 to 0x03FF is
copied from device registers and RAM to EEPROM.
This includes all registers, all configuration tables in
RAM and the primary Descriptor Table in RAM at
address 0x0200 to 0x03FF. The 1K x 16 write to EE-
PROM requires up to 83 ms.
If EE1K is low when EECOPY is asserted, the en-
tire 32K x 16 address range from 0x0 to 0x7FFF is
copied from device registers and RAM to EEPROM.
This range covers all registers, all configuration ta-
bles in RAM, the primary Descriptor Table in RAM
at address 0x0200 to 0x03FF. As long as EE1K re-
mains low when auto-initialization occurs, the 32K
x 16 programming option can initialize secondary
Descriptor Tables above address 0x0400, if used.
The 32K x 16 write to EEPROM requires up to 2.64
seconds.
address 0x0020 is first written 0x5A0F, then a
second load to 0x0020 overwrites the value just
written with 0xA0F5.