HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 37

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

Bit No. Mnemonic
12,11
6,5
13
10
9
8
7
4
IBR
-----
MERR
-----
ILCMD
SPIFAIL
LBFA, LBFB R/W
TTINT1
R/W
R/W
R/W
R/W
R/W
R.W
R.W
R/W
Reset
0
0
0
0
0
0
0
0
Function
Broadcast Command Received Interrupt.
When this bit is asserted, interrupts are globally enabled for each broad-
cast message to subaddresses in which the Descriptor Control Word
allows the IBR interrupt. When this bit is asserted, occurrence of an IBR
event causes INTMES output assertion (if the IBR bit is set in the com-
mand’s descriptor Control Word).
Not Used.
Message Error Interrupt.
When this bit is high, the INTMES interrupt output is asserted when a mes-
sage error is detected. Errors are caused by Manchester encoding prob-
lems or protocol errors. Interrupt assertion occurs whenever the terminal
sets the ME “message error” bit in the terminal’s status word. The detected
error type can be found in Message Information Word stored as a result of
message processing.
Not Used.
Illegal Command Interrupt.
Illegal commands are defined in the Illegalization Table. When enabled, the
ILCMD interrupt is asserted when the Illegalization Table bit corresponding
to the received command is logic 1. The Illegalization Table should
only contain nonzero values when “illegal command detection” is being
applied. When illegal commands are received, the terminal responds by
transmitting status word with ME “message error” flag set; no data words
are transmitted. If this ILCMD bit is high, all illegal commands cause
INTMES interrupt output assertion. See next section entitled “Pending
Interrupt Register” (below) and the section entitled “Illegalization Table” for
further information.
SPI Fail Interrupt (HI-6121 only).
The HI-6121 uses a SPI interface for host access. The device operates in
SPI Slave mode. When this bit is high, the INTHW output is asserted and
the Interrupt Log is updated each time an incorrect number of SCK clocks
occurs during SPI chip select assertion.
Loopback Fail Bus A and Loopback Fail Bus B Interrupts.
During all transmitted command responses, the device compares words
transmitted to the received and decoded words detected on the bus. When
this bit is high, the INTMES output is asserted and the Interrupt Log is
updated each time loopback detects word mismatch.
Time-Tag Interrupt 1.
If this bit is logic 1, the INTHW interrupt output is asserted and the TTINT1
bit is set in the Pending Interrupt register each time the free-running Time-
Tag counter value matches the value stored in the Time-Tag Utility Regis-
ter.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
37