HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 954

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21 Power-Down Modes
• The division ratio can be changed while the chip is operating. The clock output from the φ pin
• Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits
Bit 5
DIV
0
1
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0,
these bits select the bus master clock; when the DIV bit is set to 1, they select the division ratio of
the clock supplied to the entire chip.
Bit 2
SCK2
0
1
Rev.6.00 Sep. 27, 2007 Page 924 of 1268
REJ09B0220-0600
will also change when the division ratio is changed. The frequency of the clock output from
the φ pin in this case will be as follows:
Where: EXTAL: Crystal resonator or external clock frequency
SCK2 to SCK0.
Bit 1
SCK1
0
1
0
1
Description
When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed
mode is set
When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is
supplied to the entire chip
φ = EXTAL × n
n:
Bit 0
SCK0
0
1
0
1
0
1
—
Division ratio (n = φ/2, φ/4, or φ/8)
DIV = 0
Bus master is in high-speed
mode
Medium-speed clock is φ/2
Medium-speed clock is φ/4
Medium-speed clock is φ/8
Medium-speed clock is φ/16
Medium-speed clock is φ/32
—
(Initial value)
Description
DIV = 1
Bus master is in high-speed
mode
Clock supplied to entire chip is φ/2
Clock supplied to entire chip is φ/4
Clock supplied to entire chip is φ/8
—
—
—
(Initial value)
(Initial value)