HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 174

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HD6412320

Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 6 Bus Controller
• Idle cycle insertion
• Write buffer functions
• Bus arbitration function
• Other features
Note: * The DRAM interface, DMAC, and refresh counter are not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 144 of 1268
REJ09B0220-0600
⎯ An idle cycle can be inserted in case of an external read cycle between different areas
⎯ An idle cycle can be inserted when an external read cycle is immediately followed by an
⎯ External write cycle and internal access can be executed in parallel
⎯ DMAC * single address mode and internal access can be executed in parallel
⎯ Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC
⎯ Refresh counter (refresh timer) * can be used as an interval timer
⎯ External bus release function
external write cycle

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