HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 240

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.10
6.10.1
The chip can release the external bus in response to a bus request from an external device. In the
external bus released state, the internal bus master continues to operate as long as there is no
external access.
If an internal bus master wants to make an external access in the external bus released state, or if a
refresh request * is generated, it can issue a bus request off-chip.
The BREQOPS bit can be used to change the BREQO output pin from PF
Note: * The DRAM interface is not supported in the H8S/2321.
6.10.2
In external expansion mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the BREQ pin low issues an external bus request to the chip. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped. Even if a refresh request * is generated in the external bus released state, refresh control *
is deferred until the external bus master drops the bus request.
If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external
access in the external bus released state, or when a refresh request * is generated, the BREQO pin
is driven low and a request can be made off-chip to drop the bus request.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
Rev.6.00 Sep. 27, 2007 Page 210 of 1268
REJ09B0220-0600
Bus Release
Overview
Operation
(High) External bus release > Internal bus master external access (Low)
2
to P5
3
.