HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 1235

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

TSR0—Timer Status Register 0
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
:
:
:
—
—
7
1
—
—
6
1
—
—
5
0
Overflow Flag
R/(W) *
TCFV
0
1
4
0
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
R/(W) *
Input Capture/Output Compare Flag D
TGFD
0
1
3
0
[Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
Input Capture/Output Compare Flag C
is 0
TGRD is functioning as input capture register
0
1
R/(W) *
TGFC
2
0
[Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare
• When TCNT value is transferred to TGRC by input capture signal
DTC is 0
register
while TGRC is functioning as input capture register
R/(W) *
Input Capture/Output Compare Flag B
TGFB
0
1
Rev.6.00 Sep. 27, 2007 Page 1205 of 1268
1
0
H'FFD5
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
• When TCNT value is transferred to TGRB by input
of MRB in DTC is 0
output compare register
capture signal while TGRB is functioning as input capture
register
R/(W) *
Input Capture/Output Compare Flag A
Note: 1. The DMAC is not supported in the H8S/2321.
TGFA
0
1
0
0
[Clearing conditions]
• When DTC is activated by TGIA interrupt while
• When DMAC*
• When 0 is written to TGFA after reading
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning
• When TCNT value is transferred to TGRA by
Appendix B Internal I/O Registers
DISEL bit of MRB in DTC is 0
while DTA bit of DMABCR in DMAC*
TGFA = 1
as output compare register
input capture signal while TGRA is functioning
as input capture register
1
is activated by TGIA interrupt
REJ09B0220-0600
1
is 1
TPU0