HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 600

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HD6412320

Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 12 8-Bit Timers
12.3.3
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12.7
shows the timing of this operation.
12.3.4
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.8
shows the timing of this operation.
Rev.6.00 Sep. 27, 2007 Page 570 of 1268
REJ09B0220-0600
φ
External reset
input pin
Clear signal
TCNT
Timing of TCNT External Reset
Timing of Overflow Flag (OVF) Setting
φ
TCNT
Overflow signal
OVF
Figure 12.7 Timing of Clearance by External Reset
Figure 12.8 Timing of OVF Setting
N–1
H'FF
N
H'00
H'00

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