HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 325

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 7.31 shows an example of DREQ pin falling edge activated single address mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA single cycle ends, acceptance
Figure 7.31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer
Address bus
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DMA control
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and
the request is held.)
φ
Idle
[1]
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Section 7 DMA Controller (Not Supported in the H8S/2321)
Single
Request clear
Transfer source/
DMA single
period
destination
Acceptance resumes
Idle
[4]
Request
Bus release
Rev.6.00 Sep. 27, 2007 Page 295 of 1268
Minimum of
2 cycles
[5]
[6]
Single
DMA single
Request clear
Transfer source/
destination
period
Acceptance resumes
Idle
[7]
REJ09B0220-0600
Bus release