HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 314

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HD6412320

Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 7 DMA Controller (Not Supported in the H8S/2321)
Full Address Mode (Cycle Steal Mode): Figure 7.20 shows a transfer example in which TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the
bus is released one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Rev.6.00 Sep. 27, 2007 Page 284 of 1268
REJ09B0220-0600
Address bus
TEND
HWR
LWR
RD
φ
Bus release
Figure 7.20 Example of Full Address Mode (Cycle Steal) Transfer
DMA
read
DMA
write
Bus release
DMA
read
DMA
write
Bus release
DMA
read
Last transfer
cycle
DMA
write
DMA
dead
Bus
release

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