HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 524

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HD6412320

Manufacturer Part Number
HD6412320
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Buffer Operation
• When TGR is an output compare register
Rev.6.00 Sep. 27, 2007 Page 494 of 1268
REJ09B0220-0600
TGR0B
TGR0A
H'0000
TGR0C
TGR0A
TIOCA
Figure 10.19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details of PWM modes, see section 10.4.6, PWM Modes.
TCNT value
Transfer
H'0200
H'0200
Figure 10.19 Example of Buffer Operation (1)
H'0200
H'0450
H'0450
H'0450
H'0520
H'0520
Time

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