HD6412320 RENESAS [Renesas Technology Corp], HD6412320 Datasheet - Page 889

• Manufacturer Part Number: HD6412320
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

19.23
19.23.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when
FWE = 1, then setting the EV1 or PV1 bit. Program mode for addresses H'000000 to H'03FFFF is
entered by setting SWE1 to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1
bit. Erase mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when FWE
= 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, and
in hardware standby mode and software standby mode. The initial value is H'80 when a high level
is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is
disabled, a read will return H'00, and writes are invalid.
Writes to the SWE1 bit in FLMCR1 are valid only when FWE = 1;
writes to the ESU1, PSU1, EV1, and PV1 bits only when FWE = 1 and SWE1 = 1;
writes to the E1 bit only when FWE = 1, SWE1 = 1, and ESU1 = 1;
and writes to the P1 bit only when FWE = 1, SWE1 = 1, and PSU1 = 1.
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE
0
1
Bit 6—Software Write Enable Bit 1 (SWE1): Enables or disables flash memory programming
and erasing for addresses H'000000 to H'03FFFF. This bit should be set when setting bits 5 to 0 in
FLMCR1, EBR1 bits 7 to 0, and EBR2 bits 3 to 0.
When SWE1 = 1, the flash memory can only be read in program-verify or erase-verify mode.
Bit
Initial value :
R/W
Register Descriptions
Description
When a low level is input to the FWE pin (hardware-protected state)
When a high level is input to the FWE pin
:
:
FWE
1/0
R
7
SWE1
R/W
6
0
ESU1
R/W
5
0
PSU1
R/W
4
0
Rev.6.00 Sep. 27, 2007 Page 859 of 1268
R/W
EV1
3
0
R/W
PV1
2
0
REJ09B0220-0600
Section 19 ROM
R/W
E1
1
0
R/W
P1
0
0