MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 379

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

68HC908AZ32A — Rev 0.0
MOTOROLA
NOTE:
NOTE:
MISO — Master In/Slave Out Bit
SS — Slave Select Bit
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See
TACH[1:0] — Timer Channel I/O Bits
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See
RxD — SCI Receive Data Input Bit
Freescale Semiconductor, Inc.
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. (See
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. (See
as a slave, the DDRF0 bit in data direction register E (DDRE) has no
effect on the PTE4/SS pin.
The PTE3/TCH1–PTE2/TCH0 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTE3/TCH1–PTE2/TCH0 pins are timer channel I/O pins
or general-purpose I/O pins. (See
Control Registers
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. (See
Control Register 1
For More Information On This Product,
SS (Slave Select)
SPI Control Register
Go to: www.freescale.com
I/O Ports
on page 299).
on page 229).
on page 269). When the SPI is enabled
on page 271).
TIMA Channel Status and
Table
Table
23-5).
23-5).
Advance Information
SCI
I/O Ports
Port E
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