MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 179

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

12.4.2 Data Format
68HC908AZ32A — Rev 0.0
MOTOROLA
BREAK
$A5
START
BIT
START
START
BIT
BIT
BIT 0
BIT 0
BIT 0
Table 12-2
monitor mode.
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See
The data transmit and receive rate can be anywhere up to 28.8 kBaud.
Transmit and receive baud rates must be identical.
Monitor
1. If the high voltage (V
Modes
BIT 1
Figure 12-3. Sample Monitor Waveforms
User
Freescale Semiconductor, Inc.
the SIM asserts its COP enable output. The COP is enabled or disabled by the COPD bit
in the configuration register. (see
BIT 1
BIT 1
For More Information On This Product,
Figure 12-2. Monitor Data Format
BIT 2
Disabled
BIT 2
BIT 2
Enabled
is a summary of the differences between user mode and
Go to: www.freescale.com
COP
BIT 3
Monitor ROM (MON)
BIT 3
BIT 3
(1)
HI
) is removed from the IRQ and/or RESET pin while in monitor mode,
Table 12-2. Mode Differences
BIT 4
Vector
$FFFE
$FEFE
Reset
High
BIT 4
BIT 4
BIT 5
5.0 Volt DC Electrical Characteristics
BIT 5
BIT 5
Vector
$FFFF
$FEFF
Reset
Low
BIT 6
BIT 6
BIT 6
Functions
Figure 12-2
$FEFC
BIT 7
Vector
$FFFC
Break
High
BIT 7
BIT 7
STOP
BIT
STOP
STOP
$FEFD
Vector
$FFFD
Break
BIT
BIT
Low
and
START
NEXT
BIT
Functional Description
START
START
NEXT
NEXT
Figure
BIT
BIT
Monitor ROM (MON)
Advance Information
$FEFC
Vector
$FFFC
High
SWI
on page 446).
12-3.)
Vector
$FFFD
$FEFD
Low
SWI
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