MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 323

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

19.7 TIMB During Break Interrupts
19.8 I/O Signals
19.8.1 TIMB Clock Pin (PTD4/ATD12)
68HC908AZ32A — Rev 0.0
MOTOROLA
A break interrupt stops the TIMB counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see
on page 134).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Port D shares one of its pins with the TIMB. Port F shares two of its pins
with the TIMB. PTD4/ATD12 is an external clock input to the TIMB
prescaler. The two TIMB channel I/O pins are PTF4 and PTF5/TBCH1.
PTD4/ATD12 is an external clock input that can be the clock source for
the TIMB counter instead of the prescaled internal bus clock. Select the
PTD4/ATD12 input by writing logic 1s to the three prescaler select bits,
PS[2:0] (see
TCLK pulse width, TCLK
Freescale Semiconductor, Inc.
For More Information On This Product,
Timer Interface Module B (TIMB)
Go to: www.freescale.com
19.9.1 TIMB Status and Control
LMIN
------------------------------------ -
bus frequency
or TCLK
1
SIM Break Flag Control Register
HMIN
+
t
, is:
SU
Timer Interface Module B (TIMB)
Register). The minimum
TIMB During Break Interrupts
Advance Information
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