MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 203
MC68HC908AZ32ACFU
Manufacturer Part Number
MC68HC908AZ32ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AZ32ACFU.pdf
(468 pages)
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68HC908AZ32A — Rev 0.0
MOTOROLA
NOTE:
If the MODE bit is set, the IRQ1 pin is both falling-edge sensitive and
low-level sensitive. With MODE set, both of the following actions must
occur to clear the IRQ latch:
The vector fetch or software clear and the return of the IRQ1 pin to
logic 1 can occur in any order. The interrupt request remains pending as
long as the IRQ1 pin is at logic 0. A reset will clear the latch and the
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ1 pin is falling-edge sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
Freescale Semiconductor, Inc.
•
•
For More Information On This Product,
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to the
ACK bit in the interrupt status and control register (ISCR). The ACK
bit is useful in applications that poll the IRQ1 pin and require
software to clear the IRQ latch. Writing to the ACK bit can also
prevent spurious interrupts due to noise. Setting ACK does not
affect subsequent transitions on the IRQ1 pin. A falling edge on IRQ
that occurs after writing to the ACK bit latches another interrupt
request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and
$FFFB.
Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, the IRQ1 latch remains set.
External Interrupt Module (IRQ1)
Go to: www.freescale.com
External Interrupt Module (IRQ1)
Advance Information
IRQ Pin
203
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