MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 286

• Manufacturer Part Number: MC68HC908AZ32ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Timer Interface Module A (TIMA)
18.4.3.2 Buffered Output Compare
Advance Information
286
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE2/TCH0 pin. The TIMA
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The output compare value in the
TIMA channel 0 registers initially controls the output on the PTE2/TCH0
pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1
registers to synchronously control the output after the TIMA overflows.
At each subsequent overflow, the TIMA channel registers (0 or 1) that
control the output are the ones written to last. TASC0 controls and
monitors the buffered output compare function and TIMA channel 1
status and control register (TASC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O
pin.
Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the PTF0/TCH2 pin. The TIMA
channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIMA channel 2 status and control register
(TASC2) links channel 2 and channel 3. The output compare value in the
TIMA channel 2 registers initially controls the output on the PTF0/TCH2
pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3
registers to synchronously control the output after the TIMA overflows.
At each subsequent overflow, the TIMA channel registers (2 or 3) that
control the output are the ones written to last. TASC2 controls and
monitors the buffered output compare function, and TIMA channel 3
status and control register (TASC3) is unused. While the MS2B bit is set,
the channel 3 pin, PTF1/TCH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare
channel whose output appears on the PTF2/TCH4 pin. The TIMA
channel registers of the linked pair alternately control the output.
Setting the MS4B bit in TIMA channel 4 status and control register
(TASC4) links channel 4 and channel 5. The output compare value in the
TIMA channel 4 registers initially controls the output on the PTF2/TCH4
Freescale Semiconductor, Inc.
For More Information On This Product,
Timer Interface Module A (TIMA)
Go to: www.freescale.com
68HC908AZ32A — Rev 0.0
MOTOROLA