MC68HC908AZ32ACFU MOTOROLA [Motorola, Inc], MC68HC908AZ32ACFU Datasheet - Page 198

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MC68HC908AZ32ACFU

Manufacturer Part Number
MC68HC908AZ32ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

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Low Voltage Inhibit (LVI)
14.7 Low-Power Modes
14.7.1 Wait Mode
14.7.2 Stop Mode
Advance Information
198
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
With the LVIPWR bit in the configuration register programmed to logic 1,
the LVI module is active after a WAIT instruction.
With the LVIRST bit in the configuration register programmed to logic 1,
the LVI module can generate a reset and bring the MCU out of wait
mode.
With the LVISTOP and LVIPWR bits in the configuration register
programmed to a logic 1, the LVI module will be active after a STOP
instruction. Because CPU clocks are disabled during stop mode, the LVI
trip must bypass the digital filter to generate a reset and bring the MCU
out of stop.
With the LVIPWR bit in the configuration register programmed to logic 1
and the LVISTOP bit at a logic 0, the LVI module will be inactive after a
STOP instruction.
Note that the LVI feature is intended to provide the safe shutdown of the
microcontroller and thus protection of related circuitry prior to any
application V
intended that users operate the microcontroller at lower than specified
operating voltage V
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
DD
Low Voltage Inhibit (LVI)
voltage collapsing completely to an unsafe level. It is not
DD
.
68HC908AZ32A — Rev 0.0
MOTOROLA

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