h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 97

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

2.8.2
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are disabled in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 14,
Watchdog Timer (WDT).
Notes: 1.
RES = high
Exception-handling state
Reset State
2.
3.
Bus-released state
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 24, Power-Down State.
Reset state
End of bus
request
End of
exception
handling
*1
Figure 2.15 State Transitions
Bus
request
STBY = high, RES = low
External interrupt
Request for
exception
handling
Program execution
End of bus request
Bus request
state
Interrupt
request
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
Rev. 3.00 Jan 18, 2006 page 69 of 1044
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Hardware standby mode
Software standby mode
Power-down state
Sleep mode
REJ09B0280-0300
Section 2 CPU
*3
*2