h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 562

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h8s-2169

Manufacturer Part Number
h8s-2169
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 16 I
16.3.6
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 16.11 shows the IRIC set timing and SCL control.
Rev. 3.00 Jan 18, 2006 page 534 of 1044
REJ09B0280-0300
SCL
(master output)
SCL
(slave output)
SDA
(slave output)
SDA
(master output)
TDRE
IRIC
ICDRT
ICDRS
User processing
Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0)
IRIC Setting Timing and SCL Control
Slave receive mode Slave transmit mode
2
C Bus Interface
R/W
8
[3] IRIC
clearance
Interrupt
request
generation
[2]
A
9
[3] ICDR write
Data 1
Bit 7
Interrupt
request
generation
1
Bit 6
Data 1
2
[3] ICDR write
Bit 5
3
Bit 4
Data 1
Data 2
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
[5] IRIC
8
clearance
9
Interrupt
request
generation
A
[3]
Data 2
Bit 7
[5] ICDR write
1
Data 2
Bit 6
2

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