h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 109

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1
and cannot be modified. In modes 2 and 3, this bit has an initial value of 0, and can be read and
written.
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate the input levels at pins
MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to MD1 and
MD0. MDS1 and MDS0 are read-only bits—they cannot be written to. The mode pin (MD1 and
MD0) input levels are latched into these bits when MDCR is read.
3.2.2
SYSCR is an 8-bit readable/writable register that performs selection of system pin functions, reset
source monitoring, interrupt control mode selection, NMI detected edge selection, supporting
module pin location selection, supporting module register access control, and RAM address space
control.
Only bits 7, 6, 3, 1, and 0 are described here. For a detailed description of these bits, refer also to
the description of the relevant modules (host interface, bus controller, watchdog timer, RAM,
etc.). For information on bits 5, 4, and 2, see section 5.2.1, System Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Chip Select 2 Enable (CS2E): Specifies the location of the host interface control pin
(CS2). For details, see section 18A, Host Interface X-Bus Interface (XBS).
Bit 7
EXPE
0
1
Bit
Initial value
Read/Write
System Control Register (SYSCR)
Description
Single chip mode is selected
Expanded mode is selected
CS2E
R/W
7
0
IOSE
R/W
6
0
INTM1
R
5
0
INTM0
R/W
4
0
Rev. 3.00 Jan 18, 2006 page 81 of 1044
XRST
R
3
1
Section 3 MCU Operating Modes
NMIEG
R/W
2
0
R/W
HIE
REJ09B0280-0300
1
0
RAME
R/W
0
1