h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 934

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Appendix B Internal I/O Registers
HICR1—Host Interface Control Register 1
Rev. 3.00 Jan 18, 2006 page 906 of 1044
REJ09B0280-0300
Bit
Initial value
Slave Read/Write
Host Read/Write
LPC busy
0
1
Host interface is in transfer cycle wait state
• Bus idle, or transfer cycle not subject to processing is in progress
• Cycle type or address indeterminate during transfer cycle
[Clearing conditions] • LPC hardware reset or LPC software reset
Host interface is performing transfer cycle processing
[Setting condition]
LPCBSY
—
R
7
0
LCLK request
0
1
No LCLK restart request
[Clearing conditions] • LPC hardware reset or LPC software reset
LCLK restart request issued
[Setting condition]
• LPC hardware shutdown or LPC software shutdown
• Forced termination (abort) of transfer cycle subject to processing
• Normal termination of transfer cycle subject to processing
• Match of cycle type and address
CLKREQ
—
R
6
0
SERIRQ busy
0
1
SERIRQ transfer frame wait state
[Clearing conditions] • LPC hardware reset or LPC software reset
SERIRQ transfer processing in progress
[Setting condition]
IRQBSY
LPC software reset bit
0
1
• LPC hardware shutdown or LPC software shutdown
• SERIRQ is set to continuous mode
• There are no further interrupts for transfer to the host in quiet mode
• In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped
—
R
5
0
Normal state
[Clearing conditions] • Writing 0
LPC software reset state
[Setting condition]
LPC software shutdown bit
0
1
Normal state
[Clearing conditions] • Writing 0
LPC software shutdown state
[Setting condition]
PME output bit
HICR0
PMEE
Bit 2
LRSTB
0
1
R/W
• LPC hardware shutdown or LPC software shutdown
• End of SERIRQ transfer frame
• Start of SERIRQ transfer frame
LSMI output bit
—
HICR0
LSMIE
4
0
Bit 1
HICR1
PMEB
0
1
Bit 2
LSCI output bit
HICR0
0
1
0
1
LSCIE
• LPC hardware reset
• Writing 1 after reading LRSTB = 0
Bit 0
0
1
HICR1
LSMIB
Bit 1
0
1
0
1
PME output disabled, other function of pin enabled
PME output disabled, other function of pin enabled
PME output enabled, PME pin output goes to 0 level
PME output enabled, PME pin output is high-impedance
H'FE41
SDWNB
HICR1
LSCIB
• LPC hardware reset or LPC software reset
• LPC hardware shutdown
• LPC hardware shutdown release
• Writing 1 after reading SDWNB = 0
Bit 0
R/W
0
1
0
1
(falling edge of LPCPD signal when SDWNE = 1)
(rising edge of LPCPD signal when SDWNE = 0)
LSMI output disabled, other function of pin enabled
LSMI output disabled, other function of pin enabled
LSMI output enabled, LSMI pin output goes to 0 level
LSMI output enabled, LSMI pin output is high-impedance
—
3
0
LSCI output disabled, other function of pin enabled
LSCI output disabled, other function of pin enabled
LSCI output enabled, LSCI pin output goes to 0 level
LSCI output enabled, LSCI pin output is high-impedance
PMEB
R/W
Description
—
2
0
Description
Description
LSMIB
R/W
—
1
0
LSCIB
HIF (LPC)
R/W
—
0
0