h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 741

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Note: Use a (z3) s write pulse for additional
Notes: 1. Data transfer is performed by byte transfer.
Note 7: Write Pulse Width
Program Data Computation Chart
Number of Writes n
Original Dat
Write pulse application subroutine
Wait (z1) s, (z2) s or (z3) s
(D)
programming.
0
1
Clear PSU bit in FLMCR2
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been
4. A 128-byte area for storing program data, a 128-byte area
5. The write pulse of (z1) s or (z2) s is applied according to the progress of the programming operation. See Note 7 for the pulse widths. When writing of additional
6. See section 25.6, Flash Memory Characteristics, for the values of x, y, z1, z2, z3, , , , , , , and N.
1000
998
999
Set PSU bit in FLMCR2
Sub-routine write pulse
10
11
12
13
Clear P bit in FLMCR1
1
2
3
4
5
6
7
8
9
. .
.
Set P bit in FLMCR1
Additional program data
storage area (128 bytes)
Reprogram data storage
The lower 8 bits of the first address written to must be
H'00 or H'80. A 128-byte data transfer must be performed
even if writing fewer than 128 bytes; in this case,
H'FF data must be written to the extra addresses.
completed in the 128-byte programming loop will be
subjected to additional programming if they fail
the subsequent verify operation.
for storing reprogram data, and a 128-byte area for storing additional program data must be provided in RAM.
The reprogram and additional program data contents are modified as programming proceeds.
program data is executed, a (z3) µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Program data storage
Disable WDT
Enable WDT
area (128 bytes)
Verify Data
Wait ( ) s
area (128 bytes)
Wait (y) s
Wait ( ) s
End sub
(V)
0
1
0
1
RAM
Write Time (z) s
*6
Reprogram Data
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
. .
.
(X)
1
0
1
1
Figure 22.12 Program/Program-Verify Flowchart
*6
*5 *6
*6
*6
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Increment
address
Comments
Write 128-byte data in additional program data
Transfer reprogram data to reprogram data area *4
Store 128-byte program data in program
area in RAM consecutively to flash memory
NG
Write 128-byte data in RAM reprogram data
data area and reprogram data area
Additional program data computation
H'FF dummy write to verify address
Transfer additional program data
area consecutively to flash memory
to additional program data area
Reprogram data computation
Additional write pulse (z3) s
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Read verify data
(z1) s or (z2) s
data verification?
End of 128-byte
Program data =
Wait (x) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
Write pulse
verify data?
OK
OK
OK
m = 0?
m = 0
6
n = 1
6
Start
Additional Program Data Computation Chart
Reprogram Data
n?
OK
n?
OK
(X')
0
1
Sub-routine-call
Rev. 3.00 Jan 18, 2006 page 713 of 1044
Verify Data
NG
NG
NG
NG
(V)
0
1
0
1
*6
*6
*4
*1
See Note 7 for pulse width
*6
*6
*6
*2
*4
*3
*6
*1
*6
m = 1
Additional Program
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Data (Y)
0
1
1
1
Clear SWE bit in FLMCR1
Programming failure
Wait ( ) s
n
Additional programming executed
Additional programming not executed
Additional programming not executed
1000?
OK
REJ09B0280-0300
Section 22 ROM
Comments
NG
n
n + 1
*6