h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 649

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

The IDR registers are 8-bit read-only registers to the slave processor, and 8-bit write-only registers
to the host processor. The registers selected from the host according to the I/O address are shown
in the following table. For information on IDR3 selection, see section 18B.2.4, LPC Channel 3
Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected
register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether
the written information is a command or data.
The initial values of the IDR registers after a reset and in standby mode are undetermined.
18B.2.6 Output Data Registers (ODR1 to ODR3)
The ODR registers are 8-bit readable/writable registers to the slave processor, and 8-bit read-only
registers to the host processor. The registers selected from the host according to the I/O address
are shown in the following table. For information on ODR3 selection, see section 18B.2.4, LPC
Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register
is transferred to the host.
The initial values of the ODR registers after a reset and in standby mode are undetermined.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
0000 0000 0110
0000 0000 0110
Bit
Initial value
Slave Read/Write
Host Read/Write
Bits 15 to 4
0000 0000 0110
0000 0000 0110
Bit 7
R/W
I/O Address
I/O Address
Bit 3
0
0
0
0
—
Bit 3
0
0
R
7
Bit 2
0
1
0
1
Bit 2
0
0
Bit 6
R/W
—
R
6
Bit 1
0
0
1
1
Bit 1
0
1
Bit 5
R/W
—
R
5
Bit 0
0
0
0
0
Bit 0
0
0
Section 18B Host Interface LPC Interface (LPC)
Bit 4
R/W
—
R
4
Rev. 3.00 Jan 18, 2006 page 621 of 1044
Transfer
Cycle
I/O write
I/O write
I/O write
I/O write
Transfer
Cycle
I/O read
I/O read
Bit 3
R/W
—
R
3
Host Register Selection
IDR1 write, C/D1
IDR1 write, C/D1
IDR2 write, C/D2
IDR2 write, C/D2
Host Register Selection
ODR1 read
ODR2 read
Bit 2
R/W
—
R
2
REJ09B0280-0300
Bit 1
R/W
—
R
1
0
1
0
1
Bit 0
R/W
—
R
0