h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 619

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

18A.2.6 Status Register (STR)
STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface
processing. Bits 3, 1, and 0 are read-only bits to both the host and the slave processors.
STR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D D D D ): Receives the HA0 input when the host processor writes to IDR,
and indicates whether IDR contains data or a command.
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 18A.7.
Bit 3
C/D D D D
0
1
Bit 1
IBF
0
1
Bit
Initial value
Slave Read/Write
Host Read/Write
Note: * Only 0 can be written, to clear the flag.
Description
Contents of input data register (IDR) are data
Contents of input data register (IDR) are a command
Description
[Clearing condition]
When the slave processor reads IDR
[Setting condition]
When the host processor writes to IDR
DBU
R/W
R
7
0
DBU
R/W
R
6
0
DBU
R/W
R
5
0
Section 18A Host Interface X-Bus Interface (XBS)
DBU
R/W
R
4
0
Rev. 3.00 Jan 18, 2006 page 591 of 1044
C/D
R
R
3
0
DBU
R/W
R
2
0
REJ09B0280-0300
IBF
R
R
1
0
(Initial value)
(Initial value)
R/(W) *
OBF
R
0
0