h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 537

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the
acknowledge bit returned from the receiving device when using the I
and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,
performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received
acknowledge bit is not indicated by the ACKB bit, which is always 0.
In the H8S/2169 or H8S/2149, the DTC can be used to perform continuous transfer. The DTC is
activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other
being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of
data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the
TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge
bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge
bit is 1.
When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified
number of data transfers have been executed. Consequently, interrupts are not generated during
continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the
ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled.
Depending on the receiving device, the acknowledge bit may be significant, in indicating
completion of processing of the received data, for instance, or may be fixed at 1 and have no
significance.
Bit 4
TRS
0
1
Description
Receive mode
[Clearing conditions]
1. When 0 is written by software (in cases other than setting condition 3)
2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3)
3. When bus arbitration is lost after transmission is started in I
4. When the SW bit in DDCSWR changes from 1 to 0
Transmit mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing conditions 3 and 4)
2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3
3. When a 1 is received as the R/W bit of the first frame in I
mode
and 4)
Rev. 3.00 Jan 18, 2006 page 509 of 1044
2
C bus format is to be ignored
Section 16 I
2
C bus format slave mode
2
C bus format master
REJ09B0280-0300
2
C Bus Interface
(Initial value)