h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 555

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

16.3.3
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data.
The receive procedure and operations by which data is sequentially received in synchronization
with ICDR read operations, are described below.
[1] Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the
[2] When ICDR is read (dummy data read), reception is started and the receive clock is output,
Reading from ICDR and clearing of the IRIC flag must be executed continuously so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is
cleared, the end of transfer cannot be identified.
Precaution:
Data set timing to
ICDR
Incorrect operation
(ICDR writing
prohibited)
User processing
(Slave output)
Figure 16.7 Example of Master Transmit Mode Operating Timing (MLS = WAIT = 0)
(Master output)
(Master output)
WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).
and data is received, in synchronization with the internal clock. To indicate the wait, clear
the IRIC flag to 0.
SDA
ICDR
IRTR
IRIC
SDA
SCL
Master Receive Operation
[4] Write 1 to BBSY
Start condition generation
and 0 to SCP
(start condition
issuance)
[5]
operation
Normal
[6] ICDR write
Address + R/W
Bit 7
1
Bit 6
2
[6] IRIC clear
Bit 5
Slave address
3
Bit 4
4
Bit 3
5
Rev. 3.00 Jan 18, 2006 page 527 of 1044
Bit 2
6
Bit 1
7
R/W
Bit 0
Section 16 I
8
[7]
A
9
[9] ICDR write
REJ09B0280-0300
2
C Bus Interface
Data 1
[9] IRIC clear
Bit 7
1
Data 1
Bit 6
2