h8s-2169 Renesas Electronics Corporation., h8s-2169 Datasheet - Page 13

• Manufacturer Part Number: h8s-2169
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Overview........................................................................................................................... 101
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 105
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
Interrupt Sources............................................................................................................... 115
5.3.1
5.3.2
5.3.3
Address Breaks ................................................................................................................. 121
5.4.1
5.4.2
5.4.3
5.4.4
Interrupt Operation............................................................................................................ 124
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Usage Notes ...................................................................................................................... 134
5.6.1
5.6.2
5.6.3
DTC Activation by Interrupt............................................................................................. 136
5.7.1
5.7.2
5.7.3
Features................................................................................................................ 101
Block Diagram ..................................................................................................... 102
Pin Configuration................................................................................................. 103
Register Configuration......................................................................................... 104
System Control Register (SYSCR) ...................................................................... 105
Interrupt Control Registers A to C (ICRA to ICRC)............................................ 106
IRQ Enable Register (IER) .................................................................................. 107
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 107
IRQ Status Register (ISR).................................................................................... 108
Keyboard Matrix Interrupt Mask Register (KMIMR) ......................................... 110
Keyboard Matrix Interrupt Mask Register A (KMIMRA) Wakeup Event
Interrupt Mask Registr B (WUEMRB) ................................................................ 110
Address Break Control Register (ABRKCR)....................................................... 113
Break Address Registers A to C (BARA to BARC) ............................................ 114
External Interrupts ............................................................................................... 115
Internal Interrupts................................................................................................. 117
Interrupt Exception Vector Table ........................................................................ 118
Features................................................................................................................ 121
Block Diagram ..................................................................................................... 121
Operation ............................................................................................................. 122
Usage Notes ......................................................................................................... 122
Interrupt Control Modes and Interrupt Operation ................................................ 124
Interrupt Control Mode 0 ..................................................................................... 127
Interrupt Control Mode 1 ..................................................................................... 129
Interrupt Exception Handling Sequence .............................................................. 132
Interrupt Response Times .................................................................................... 133
Contention between Interrupt Generation and Disabling..................................... 134
Instructions that Disable Interrupts ...................................................................... 135
Interrupts during Execution of EEPMOV Instruction.......................................... 135
Overview.............................................................................................................. 136
Block Diagram ..................................................................................................... 136
Operation ............................................................................................................. 137
.......................................................................................... 101
Rev. 3.00 Jan 18, 2006 page xiii of xxviii