cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 79

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
28237-DSH-001-C
3.3.2.4 Status Queue
Interrupt Delay
Status Queue Interrupt Delay has been added in order to reduce the interrupt
processing load on the host. This is valuable in a Network Interface Card
(NIC)-based solution, where the SAR resides in an environment in which the host
is not dedicated to datacom processing. Both a timer holdoff mechanism and an
event counter mechanism are implemented and work in parallel. The timer
holdoff mechanism uses the ALARM1 and CLOCK register resources to
implement an interval timer. Interrupts due to status queue writes are delayed
until the timer expires. The event counter mechanism delays the assertion of the
interrupt due to status queue writes until a fixed number of status queue writes
have occurred. Both mechanisms work in parallel (not in series) if enabled, so that
either mechanism needs to expire before the interrupt propagates to the output
pin. Interrupts due to conditions other than status queue writes are not delayed.
Timer Holdoff Mechanism
The timer holdoff mechanism is enabled by setting INT_DELAY (EN_TIMER)
to a logic high. The ALARM1 register is set to a value that holds off the interrupt
for a specified period of time. The user initializes the CLOCK register to 0. When
the value in the CLOCK register is greater than the value in the ALARM1
register, status queue interrupts are allowed to propagate to the interrupt pin,
HINT*.
Event Counter Mechanism
The event counter mechanism is enabled by setting INT_DELAY
(EN_STAT_CNT) to a logic high. An internal counter is implemented that counts
the number of status queue write events. The number of events before opening the
interrupt window is programmable using the INT_DELAY(STAT_CNT) field.
The window is closed for STAT_CNT number of events. When the internal
counter has reached the value of STAT_CNT, the interrupt window is opened,
which allows the interrupt to propagate to the output pin. The counter is reset
when the status registers are read and the interrupt output goes inactive.
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3.3 Write-only Control and Status
3.0 Host Interface
3-9