cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 347

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Table 15-9. Table of Values for General Control Register Initialization (2 of 3)
28237-DSH-001-C
CONFIG1
(Configuration Register 1)
INT_DELAY
(Interrupt Delay Register)
HOST_ST_WR
(Host Status Write Register)
HOST_ISTAT1
(Host Interrupt Status Register 1)
HOST_ISTAT0
(Host Interrupt Status Register 0)
LP_ISTAT1
(Local Interrupt Status Register 1)
LP_ISTAT0
(Local Interrupt Status Register 0)
HOST_IMASK1
(Host Interrupt Mask Register 1)
Register
PHY_STROBE_IO
PHY_WAIT
PHY_RST
FR_LOOP
UTOPIA_MODE
MULTI_PHY
UTOP16
NUM_PORTS[2:0]
SLAVE_ADDR[4:0]
TAG_SIZE[3:0]
PHYBANK[4:0]
TX_FIFO_FLUSH_EN
INCFIFO_SZ
NEW_PMOAM
TIMER_LOC
EN_TIMER
EN_STAT_CNT
STAT_CNT[7:0]
RSM_HS_WRITE
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
Mindspeed Technologies
Field
0x8700FC07
Initialized
Value
0x35
—
—
—
—
—
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
™
15.0 SAR Initialization—Example Tables
Low for operation with Mindspeed framers.
Low for operation with Mindspeed framers.
Sets PRST* to logic high.
Loopback disabled.
Cell handshake.
Multi-PHY operation disabled.
UTOPIA 16-bit interface is enabled.
Multi-PHY disabled.
When in Master non-Multi-PHY mode, this
is the address present on both TxADDR and
RxADDR.
N/A
Physical Chip Bank Select. This value is
placed on PADDR[12:8] when a PHY
control access occurs.
Tx FIFO flush mechanism disabled.
Incoming DMA FIFO buffer size enables to
8 KB.
Logic high enables the new PM OAM
mechanism is enabled per ITU-T
Recommendation I.610, June 98.
Interrupt hold-off timer used with HINT*.
Disable status queue interrupt timer delay.
Enable status queue interrupt counter delay.
Interrupt delay counter set to 53.
Read twice after SAR reset.
Read twice after HOST_ST_WR reset.
Read twice after HOST_ISTAT1 reset.
Read twice after SAR reset.
Read twice after LP_ISTAT1 reset.
Enable all errors to cause an interrupt.
Notes
15.4 General Initialization
15-15